MAX3815 Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

MAX3815

TMDS Digital Video Equalizer for DVI/HDMI Cables

Maxim Integrated 

TMDS Digital Video Equalizer for DVI/HDMI

Cables

Pin Description (continued)

PIN

20, 23, 24,

25, 28, 29,

32, 33, 36,

37, 42

21

22

26

27

30

31

34

35

39

40

45–48

EP

NAME

FUNCTION

GND

Ground

RXC_OUT-

RXC_OUT+

RX2_OUT+

RX2_OUT-

Negative Clock Output, CML

Positive Clock Output, CML

Positive Data Output, CML

Negative Data Output, CML

RX1_OUT+

RX1_OUT-

RX0_OUT+

Positive Data Output, CML

Negative Data Output, CML

Positive Data Output, CML

RX0_OUT- Negative Data Output, CML

OUTLEVEL Output-Level Control Input, LVTTL. This input sets the output amplitude to the standard DVI level

(1000mVP-P) when high, and sets the output amplitude to 1/2 the DVI level (500mVP-P) when low.

OUTON

Output-Enable Control Input, LVTTL. This input enables the CML outputs when forced low and sets a

differential logic zero when forced high.

N.C.

No Connection

Exposed Pad Ground. The exposed pad must be soldered to the circuit-board ground for proper

thermal and electrical operation.

Detailed Description

The MAX3815 TMDS equalizer accepts differential CML

input data at rates of 250Mbps up to 1.65Gbps (individ-

ual channel data rate). It automatically adjusts to atten-

uation levels of up to 40dB at 825MHz due to

skin-effect losses in copper cable. It consists of four

CML input buffers, a loss-of-clock signal detector, three

independent adaptive equalizers, four limiting ampli-

fiers, and four output buffers (Figure 1).

CML Input Buffers and Output Drivers

The input buffers and the output drivers are implement-

ed using current-mode logic (CML) (see Figures 3 and

4). The output drivers are open-collector and can be

turned off with the OUTON pin, or can be set to output

a one-half amplitude signal (500mVP-P differential)

using the OUTLEVEL pin. For details on interfacing with

CML, refer to Maxim Application Note HFAN-01.0:

Introduction to LVDS, PECL, and CML.

Loss-of-Clock Signal Detector

The loss-of-clock signal detector indicates a loss-of-

clock signal at the CLKLOS pin.

Adaptive Equalizer

The three data channels each contain an independent

adaptive equalizer. Each channel analyzes the incom-

ing signal and determines the amount of equalization to

apply.

Limiting Amplifier

The limiting amplifier amplifies the signal from the

adaptive equalizer and truncates the top and bottom of

the waveform to provide a clean high- and low-level

signal to the output drivers.

Applications Information

Typical shielded twisted pair (STP) and unshielded

twisted pair (UTP) cables exhibit skin-effect losses,

which attenuate the high-frequency spectrum of a

TMDS signal, eventually causing data errors or even

closing the signal eye altogether given a long enough

cable. The MAX3815 recovers the data and opens the

signal eye through compensating equalization.

The basic TMDS interface is composed of four differen-

tial serial links: three links carry serial data up to

1.65Gbps each, and the fourth is a one-tenth-rate

(0.1x) clock that operates up to 165MHz. TMDS, as with

6 _______________________________________________________________________________________

Share Link: