MAX3691ECJ-T Ver la hoja de datos (PDF) - Maxim Integrated

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MAX3691ECJ-T

+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs

Maxim Integrated 

+3.3V, 622Mbps, SDH/SONET 4:1 Serializer

with Clock Synthesis and LVDS Inputs

__________Applications Information

Alternative PECL-Output Termination

Figure 3 shows alternative PECL output-termination

methods. Use Thevenin-equivalent termination when a

(VCC - 2V) termination voltage is not available. If AC

coupling is necessary, be sure that the coupling capac-

itor is placed following the 50Ω or Thevenin-equivalent

DC termination.

Layout Techniques

For best performance, use good high-frequency layout

techniques. Filter voltage supplies and keep ground

connections short. Use multiple vias where possible.

Also, use controlled-impedance transmission lines to

interface with the MAX3691 clock and data inputs and

outputs.

__________________Pin Configuration

TOP VIEW

GND

25

RCLK+

26

RCLK-

27

VCC

28

VCC

29

PCLKI+

30

PCLKI-

31

GND

32

MAX3691

16

VCC

15

SD+

14

SD-

13

VCC

12

VCC

11

PCLKO+

10

PCLKO-

9

GND

MAX3691

SD+

SD-

+3.3V

130Ω

130Ω

Z0 = 50Ω

Z0 = 50Ω

82Ω

PECL

INPUTS

82Ω

TQFP

___________________Chip Information

TRANSISTOR COUNT: 1633

MAX3691

SD+

Z0 = 50Ω

SD-

Z0 = 50Ω

HIGH-

IMPEDENCE

INPUTS

50Ω

50Ω

VCC - 2V

Figure 3. Alternative PECL-Output Termination

_______________________________________________________________________________________ 7

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