MAX3691ECJ-T Ver la hoja de datos (PDF) - Maxim Integrated

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MAX3691ECJ-T

+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs

Maxim Integrated 

+3.3V, 622Mbps, SDH/SONET 4:1 Serializer

with Clock Synthesis and LVDS Inputs

____________________________Typical Operating Characteristics (continued)

(VCC = +3.0V to +3.6V, differential LVDS loads = 100Ω, unless otherwise noted.)

PCLKO-to-PCLKI SKEW

vs. TEMPERATURE

6

SERIAL-DATA OUTPUT EYE DIAGRAM

(622Mbps, 27-1 PRBS)

1.21V

908mV

SERIAL-DATA OUTPUT JITTER

4

OC-12

SONET MASK

2

10mV/

div

62mV/

0

div

fRCLK = 155.52MHz

-2

-4

0.59V

-50 -25 0 25 50 75 100

TEMPERATURE (°C)

161ps/div

808mV

Mean 23.88ns

RMS∆ 8.418ps

PkPk 70.2ps

10ps/div

µ±1σ 68.774%

µ±2σ 95.534%

µ±3σ 99.738%

______________________________________________________________Pin Description

PIN

NAME

1, 3, 5, 7 PD0+ to PD3+

2, 4, 6, 8 PD0- to PD3-

9, 17, 18,

19, 24,

25, 32

GND

10

PCLKO-

11

PCLKO+

12, 13, 16,

20, 21,

VCC

28, 29

14

SD-

15

SD+

FUNCTION

Noninverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.

Inverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.

Ground

Inverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit.

Noninverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit.

+3.3V Supply Voltage

Inverting PECL Serial-Data Output

Noninverting PECL Serial-Data Output

22

FIL-

Filter Capacitor Input. See Typical Operating Circuit for external-component connections.

23

FIL+

Filter Capacitor Input. See Typical Operating Circuit for external-component connections.

26

RCLK+

Noninverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock

(155.52MHz) to the RCLK inputs.

27

RCLK-

Inverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock (155.52MHz)

to the RCLK inputs.

30

PCLKI+

Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the

PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.

31

PCLKI-

Inverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI

inputs. Note that data is updated on the positive transition of the PCLKI signal.

4 _______________________________________________________________________________________

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