MAX3680A Ver la hoja de datos (PDF) - Maxim Integrated

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MAX3680A

+3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs

Maxim Integrated 

+3.3V, 622Mbps, SDH/SONET

1:8 Deserializer with TTL Outputs

PECL Inputs

The serial data and clock PECL inputs (SD+, SD-,

SCLK+, SCLK-) require 50Ω termination to (VCC - 2V)

when interfacing with a PECL source (see Alternative

PECL Input Termination).

Applications Information

Alternative PECL Input Termination

Figure 4 shows alternative PECL input-termination

methods. Use Thevenin-equivalent termination when a

(VCC - 2V) termination voltage is not available. If AC

coupling is necessary, such as when interfacing with

an ECL-output device, use the ECL AC-coupling termi-

nation.

Layout Techniques

For best performance, use good high-frequency layout

techniques. Filter voltage supplies and keep ground

connections short. Use multiple vias where possible.

Also, use controlled impedance transmission lines to

interface with the MAX3680 data inputs.

Pin Configuration

TOP VIEW

VCC 1

VCC 2

SD+ 3

SD- 4

VCC 5

SCLK+ 6

SCLK- 7

VCC 8

GND

(N.C.)

9

SYNC

(N.C.)

10

GND 11

GND 12

PCLK 13

VCC 14

() MAX3680A ONLY.

MAX3680/

MAX3680A

SSOP

28 PD7

27 GND

26 PD6

25 VCC

24 PD5

23 GND

22 PD4

21 PD3

20 GND

19 PD2

18 VCC

17 PD1

16 GND

15 PD0

THEVENIN-EQUIVALENT TERMINATION

+3.3V

130Ω

ZO = 50Ω

130Ω

MAX3680/

MAX3680A

ZO = 50Ω

PECL

INPUTS

82Ω

82Ω

+3.3V

ECL AC-COUPLING TERMINATION

ZO = 50Ω

1.6k

1.6k

50Ω

ZO = 50Ω -2V

MAX3680/

MAX3680A

PECL

INPUTS

50Ω

2.7k

2.7k

-2V

Figure 4. Alternative PECL Input Termination

Chip Information

TRANSISTOR COUNT: 1346

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