MAX3680 Ver la hoja de datos (PDF) - Maxim Integrated
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MAX3680 Datasheet PDF : 8 Pages
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+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
Pin Description
PIN
MAX3680 MAX3680A
1, 2, 5, 8,
14, 18, 25
1, 2, 5, 8,
14, 18, 25
NAME
VCC
+3.3V Supply Voltage
FUNCTION
3
3
SD+ Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive
transition.
4
4
SD- Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
6
7
9, 11, 12,
16, 20, 23,
27
6
7
11, 12, 16,
20, 23, 27
SCLK+ Noninverting PECL Serial Clock Input
SCLK- Inverting PECL Serial Clock Input
GND Ground
10
—
13
15, 17, 19,
21, 22, 24,
26, 28
—
9, 10
13
15, 17, 19,
21, 22, 24,
26, 28
SYNC
N.C.
PCLK
TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data
alignment by dropping one bit in the serial input data stream.
No Connection
TTL Parallel Clock Output
PD0–PD7
TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the
relationship between serial-data-bit position and output-data-bit assignment.
Detailed Description
The MAX3680/MAX3680A deserializer uses an 8-bit
shift register, 8-bit parallel output register, 3-bit counter,
PECL input buffers, and TTL input/output buffers to
convert 622Mbps serial data to 8-bit-wide, 77Mbps par-
allel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel output
clock (PCLK) by dividing down the serial clock frequen-
cy. The PCLK signal is used to clock the parallel output
register. During normal operation, the counter divides the
SCLK frequency by eight, causing the output register to
latch every eight bits of incoming serial data.
The MAX3680 synchronization input (SYNC) is used for
data realignment and reframing. When the SYNC signal
is pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
SD+
PECL
SD-
SCLK+
PECL
SCLK-
SYNC
TTL
PD7
TTL
8-BIT
SHIFT
REGISTER
PD6
TTL
PD5
TTL
PD4
TTL
8-BIT
PARALLEL
OUTPUT
REGISTER
TTL
PD3
PD2
TTL
MAX3680/
MAX3680A
PD1
TTL
TTL
PD0
3-BIT
COUNTER
PCLK
TTL
Figure 1. Functional Diagram
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