MAX3270(1995) Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

MAX3270
(Rev.:1995)

155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector

Maxim Integrated 

155Mbps/622Mbps Clock Recovery and

Data Retiming IC with Fully Integrated

Phase/Frequency Detector

_______________Detailed Description

The block diagram of Figure 1 shows the MAX3270’s

architecture. The phase-locked loop (PLL) consists of a

phase/frequency detector (PFD), a loop filter amplifier,

and a voltage-controlled oscillator (VCO).

Phase Detector

The phase detector produces a voltage proportional to

the phase difference of the incoming data and the out-

put of the recovered clock. Because of its feedback

nature, the PLL will drive the error voltage to zero, mak-

ing the phase difference zero and aligning the recov-

ered clock to the incoming data. An external

phase-adjustment pin (PHADJ) allows the user to vary

phase alignment.

Frequency Detector

A frequency detector is also incorporated into the PLL.

Frequency detection aids in the acquisition of the input

data; this frequency-aided acquisition is necessary dur-

ing start-up conditions, since the input data stream and

VCO difference frequency may be outside the PLL

bandwidth. The input data stream is sampled by quad-

rature components of the VCO clock, generating a dif-

ference frequency. Depending on the rotation of the

difference frequency, the PFD will drive the VCO so that

the difference frequency is driven to zero. Once fre-

quency acquisition is obtained, the frequency detector

will return to a neutral state.

Loop Filter and VCO

The PLL is a second-order transfer function whose

bandwidth is set by the loop filter. The VCO is integrat-

ed into the PLL and always operates at 622MHz. The

center frequency is tightly controlled by laser trimming,

limiting frequency drift when lock is lost. 155Mbps or

622Mbps mode is selected by the clock-rate select

(CRS) pin. CRS selects the inputs to multiplexer MUX2.

The internal VCO can be bypassed with an external

clock applied to the EXC input. The external clock

select (EXCS) controls the input selections to multiplex-

ers MUX1 and MUX2.

PHADJ VR FILP

FILN FM

SDIP

DQ

SDIN

CLK

PHASE/FREQ

DETECTOR

FILTER

VCO

DIVIDE-

AMP

622.08MHz

BY-4

CLK

RST

MAX3270

MUX 3

0

OUTPUT

1

MUX 2

1

0

MUX 1

155MHz

0

INPUT

622MHz

1

100k

ECL RDOP RECOVERED

RDON DATA

100k

ECL

CRP

38/155MHz

100k

ECL RCOP RECOVERED

CLOCK

RCON

EXCS

EXC

RST

CRS

Figure 1. Block Diagram

_______________________________________________________________________________________ 7

Share Link: