MAX2120 Ver la hoja de datos (PDF) - Maxim Integrated
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Fabricante
MAX2120 Datasheet PDF : 21 Pages
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Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
Detailed Description
Register Description
The MAX2120 includes 12 user-programmable registers
and 2 read-only registers. See Table 1 for register con-
Table 1. Register Configuration
figurations. The register configuration of Table 1 shows
each bit name and the bit usage information for all regis-
ters. Note that all registers must be written after and no
earlier than 100µs after the device is powered up.
MSB
LSB
REG REGISTER READ/ REG
NO
NAME WRITE ADDRESS
DATA BYTE
D[7]
D[6]
D[5]
D[4]
D[3]
D[2] D[1] D[0]
1
N-Divider
MSB
Write
0x00
X
N[14]
N[13]
N[12]
N[11] N[10] N[9] N[8]
2
N-Divider
LSB
Write
0x01
N[7]
N[6]
N[5]
N[4]
N[3]
N[2] N[1] N[0]
3
Charge
Pump
Write
0x02
CPMP[1] CPMP[0] CPLIN[1] CPLIN[0]
0
0
0
0
X
X
X
X
4 Not Used Write 0x03
X
X
X
X
X
X
X
X
5 Not Used Write 0x04
X
X
X
X
X
X
X
X
XTAL
6
Divider/ Write 0x05
XD[2]
XD[1]
XD[0]
R[4]
R-Divider
R[3]
R[2] R[1] R[0]
7
PLL
Write 0x06
D24
CPS
ICP
X
X
X
X
X
8
VCO
Write 0x07
VCO[4] VCO[3] VCO[2]
VCO[1]
VCO[0] VAS ADL ADE
9
LPF
Write 0x08
LPF[7]
LPF[6]
LPF[5]
LPF[4]
LPF[3] LPF[2] LPF[1] LPF[0]
10
Control Write 0x09
STBY
X
PWDN
0
X
BBG[3] BBG[2] BBG[1] BBG[0]
11 Shutdown Write 0x0A
X
PLL
DIV
VCO
BB RFMIX RFVGA FE
0
0
0
0
0
0
0
12
Test
Write
0x0B
CPTST[2] CPTST[1] CPTST[0]
0
0
0
X
TURBO
1
LD
LD
LD
MUX[2] MUX[1] MUX[0]
0
0
0
13
Status
Byte-1
Read
0x0C
POR
VASA
VASE
LD
X
X
X
X
14
Status
Byte-2
Read
0x0D VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
0 = Set to “0” for factory-tested operation.
1 = Set to “1” for factory-tested operation.
X = Don’t care.
Table 2. N-Divider MSB Register
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
X
7
X
N[14:8]
6–0
0000011
Table 3. N-Divider LSB Register
FUNCTION
Don’t care.
Sets the most significant bits of the PLL integer-divide number (N).
Default value is N = 950 decimal. N can range from 16 to 2175.
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
N[7:0]
7–0
10110110 Sets the least significant bits of the PLL integer-divide number (N).
Default value is N = 950 decimal. N can range from 16 to 2175.
10 ______________________________________________________________________________________
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