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MAX1661

Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface

Maxim Integrated 

Serial-to-Parallel/Parallel-to-Serial Converters and

Load-Switch Controllers with SMBus Interface

R/W BIT

CLOCKED

INTO SLAVE

ACKNOWLEDGE BIT

CLOCKED

INTO MASTER

MOST SIGNIFICANT

BIT OF DATA

CLOCKED INTO MASTER

SMBCLK • • •

SMBDATA • • •

SLAVE PULLING

SMBDATA LOW

tDV

tDV

Figure 3. SMB Serial-Interface Timing—Acknowledge and Data Valid

ADDRESS

MSB

START

ADDRESS

LSB

SLAVE

ACKNOWLEDGE

I/O

LATCHED

DATA

R/W BIT

MSB

SLAVE

ACKNOWLEDGE

(ACK)

DATA LSB

SMBCLK

SMBDATA

(NOTE 1)

tSU:I/O

NOTE 1: THE SETUP AND HOLD TIMING LIMITS ARE ABSOLUTE LIMITS

(15µs MIN AND 0µs MIN, RESPECTIVELY) AND DO NOT NECESSARILY

CORRESPOND TO A PARTICULAR CLOCK EDGE.

Figure 4. I/O Read Timing Diagram

tHD:I/O

(NOTE 1)

THSD DATA3 DATA2 DATA1

SLAVE PULLS

SMBDATA LOW

4 ZEROS (NOT USED)

rupt, the host (Bus Master) interrogates the bus slave

devices via a special receive-byte operation that

includes the alert response address. The data returned

by this receive-byte operation is the address of the

offending slave device. The interrupt pointer address

can activate several different slave devices simultane-

ously. If more than one slave attempts to respond, bus

arbitration rules apply, with the lowest address code

going first. The other device(s) will not generate an

acknowledge and will continue to hold the ALERT line

low or repeat the START-STOP interrupt until serviced.

Clearing Interrupts via Alert Response

When a fault occurs, ALERT asserts and latches low. If

the fault is momentary and disappears before the

device is serviced, ALERT remains asserted. Normally,

the master sends out the Alert Response address fol-

lowed by a read bit (00011001). ALERT clears when

the device responds by successfully putting its

address on the bus. Reading the Alert Response

address is the only method for clearing hardware

and software interrupt latches. Clearing the interrupt

has no effect on the state of the status registers.

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