MAX11046BECB-T Ver la hoja de datos (PDF) - Maxim Integrated
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MAX11046BECB-T Datasheet PDF : 20 Pages
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4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
Pin Description
PIN
TQFP
TQFN
1
56
2
1
3
2
4
3
5
4
6
5
7
6
8, 22, 59 7, 21, 50
9, 21, 60 8, 20, 51
10
9
11
10
12
11
13
12
14
13
15
14
16
15
17
16
18
17
NAME
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DGND
DVDD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
EOC
FUNCTION
16-Bit Parallel Data Bus Digital Out Bit 14
16-Bit Parallel Data Bus Digital Output Bit 13
16-Bit Parallel Data Bus Digital Output Bit 12
16-Bit Parallel Data Bus Digital Output Bit 11
16-Bit Parallel Data Bus Digital Output Bit 10
16-Bit Parallel Data Bus Digital Output Bit 9
16-Bit Parallel Data Bus Digital Output Bit 8
Digital Ground
Digital Supply. Bypass to DGND with a 0.1μF capacitor at each DVDD input.
16-Bit Parallel Data Bus Digital Output Bit 7
16-Bit Parallel Data Bus Digital Output Bit 6
16-Bit Parallel Data Bus Digital Output Bit 5
16-Bit Parallel Data Bus Digital Output Bit 4
16-Bit Parallel Data Bus Digital I/O Bit 3
16-Bit Parallel Data Bus Digital I/O Bit 2
16-Bit Parallel Data Bus Digital I/O Bit 1
16-Bit Parallel Data Bus Digital I/O Bit 0
Active-Low, End-of-Conversion Output. EOC goes low when a conversion is completed.
EOC goes high when a conversion is initiated.
Convert Start Input. The rising edge of CONVST ends sample and starts a conversion on
19
18
CONVST the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST
mode = 0.
20
23, 28, 32,
38, 43, 49,
53, 58
24, 29, 35,
46, 52, 57
25, 30, 36,
45, 51, 56
19
23, 27, 33,
38, 44, 48
24, 30,
41, 47
25, 31,
40, 46
SHDN
Shutdown Input. If SHDN is held high, the entire device will enter and stay in a low-current
state. Contents of the configuration register are not lost when in the shutdown state.
AGNDS Signal Ground. Connect all AGND and AGNDS inputs together.
AVDD Analog Supply Input. Bypass AVDD to AGND with a 0.1μF capacitor at each AVDD input.
AGND Analog Ground. Connect all AGND inputs together.
26, 55
—
RD C_S E NS E
Reference Buffer Sense Feedback. Connect to RDC plane. Internally connected on the
56-pin TQFN parts
27, 33, 40,
48, 54
31
34
37
39
41
22, 28,
35, 43, 49
26
29
32
34
36
RDC
CH0
CH1
CH2
CH3
REFIO
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at
least a 80μF total capacitance. See the Layout, Grounding, and Bypassing section.
Channel 0 Analog Input
Channel 1 Analog Input
Channel 2 Analog Input
Channel 3 Analog Input
External Reference Input/Internal Reference Output. Place a 0.1μF capacitor from REFIO
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