M25P05-VMN6T Ver la hoja de datos (PDF) - STMicroelectronics

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M25P05-VMN6T

512 Kbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface

STMicroelectronics 

Figure 10. Read Status Register (RDSR) Sequence

M25P05

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C

Instruction

D

Status Register Out

Status Register Out

High Impedance

Q

76543210765432107

MSB

MSB

AI02031C

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction al-

lows the Status Register to be read. The Status

Register may be read at any time, even while a

Program, Erase or Write Status Register cycle is in

progress. When one of these cycles is in progress,

it is recommended to check the Write In Progress

(WIP) bit before sending a new instruction to the

device. It is also possible to read the Status Reg-

ister continuously, as shown in Figure 10.

Table 5. Status Register Format

b7

b0

SRWD 0 0 0 BP1 BP0 WEL WIP

Note: 1. SRWD, BP1 and BP0 are non-volatile read and write bits.

2. WEL and WIP are volatile read-only bits (WEL is set and

reset by specific instructions; WIP is automatically set

and reset by the internal logic of the device).

The status and control bits of the Status Register

are as follows:

WIP bit. The Write In Process (WIP) bit indicates

whether the memory is busy with a Write Status

Register, Program or Erase cycle. When set to 1,

such a cycle is in progress, when reset to 0 no

such cycle is in progress.

WEL bit. The Write Enable Latch (WEL) bit indi-

cates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is

set, when set to 0 the internal Write Enable Latch

is reset and no Write Status Register, Program or

Erase instruction is accepted.

BP1, BP0 bits. The Block Protect (BP1, BP0) bits

are non-volatile. They define the size of the area to

be software protected against Program and Erase

instructions. These bits are written with the Write

Status Register (WRSR) instruction. When both of

the Block Protect (BP1, BP0) bits are set to 1, the

whole memory is protected against Page Program

(PP) and Sector Erase (SE) instructions. The Bulk

Erase (BE) instruction is executed if, and only if,

both Block Protect (BP1, BP0) bits are 0. This is

summarized in Table 2. The Block Protect (BP1,

BP0) bits can be written provided that the Hard-

ware Protected mode has not been set.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected mode (when the Status Register Write

Disable (SRWD) bit is set to 1, and Write Protect

(W) is driven Low). In this mode, the non-volatile

bits of the Status Register (SRWD, BP1, BP0) be-

come read-only bits and the Write Status Register

(WRSR) instruction is no longer accepted for exe-

cution.

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