M25P05-VMN6T Ver la hoja de datos (PDF) - STMicroelectronics

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M25P05-VMN6T

512 Kbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface

STMicroelectronics 

M25P05

Figure 8. Write Enable (WREN) Sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI02281D

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 8)

sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set pri-

or to every Page Program (PP), Sector Erase

(SE), Bulk Erase (BE) and Write Status Register

(WRSR) instruction.

The Write Enable (WREN) instruction is entered

by driving Chip Select (S) Low, sending the in-

struction code, and then driving Chip Select (S)

High.

Figure 9. Write Disable (WRDI) Sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI03750C

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 9)

resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by

driving Chip Select (S) Low, sending the instruc-

tion code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under

the following conditions:

– Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction com-

pletion

– Page Program (PP) instruction completion

– Sector Erase (SE) instruction completion

– Bulk Erase (BE) instruction completion

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