M24C64-WMW6 Ver la hoja de datos (PDF) - STMicroelectronics
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M24C64-WMW6 Datasheet PDF : 19 Pages
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Figure 8. Read Mode Sequences
CURRENT
ADDRESS
READ
ACK
NO ACK
DEV SEL
DATA OUT
R/W
M24C64, M24C32
RANDOM
ADDRESS
READ
ACK
ACK
ACK
ACK
NO ACK
DEV SEL *
BYTE ADDR BYTE ADDR
DEV SEL *
DATA OUT
R/W
R/W
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
ACK
ACK
DEV SEL
DATA OUT 1
R/W
ACK
NO ACK
DATA OUT N
ACK
ACK
ACK
ACK
ACK
DEV SEL *
BYTE ADDR BYTE ADDR
DEV SEL *
DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105C
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.
internal address counter. The counter is then in-
cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8, with-
out acknowledging the byte output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
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