M24C64-WMW6 Ver la hoja de datos (PDF) - STMicroelectronics

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M24C64-WMW6

64/32 Kbit Serial IC Bus EEPROM

STMicroelectronics 

M24C64, M24C32

Figure 5. Write Mode Sequences with WC=1 (data write inhibited)

WC

BYTE WRITE

ACK

ACK

ACK

NO ACK

DEV SEL

BYTE ADDR BYTE ADDR

DATA IN

R/W

WC

PAGE WRITE

WC (cont'd)

PAGE WRITE

(cont'd)

ACK

ACK

ACK

NO ACK

DEV SEL

BYTE ADDR BYTE ADDR DATA IN 1

DATA IN 2

R/W

NO ACK

NO ACK

DATA IN N

byte address counter (the 5 least significant bits

only) is incremented. The transfer is terminated by

the master generating a STOP condition.

When the master generates a STOP condition im-

mediately after the Ack bit (in the “10th bit” time

slot), either at the end of a byte write or a page

write, the internal memory write cycle is triggered.

A STOP condition at any other time does not trig-

ger the internal write cycle.

During the internal write cycle, the SDA input is

disabled internally, and the device does not re-

spond to any requests.

AI01120B

6/19

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