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IS25C01

1K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

Integrated Silicon Solution 

IS25C01

ISSI ®

WRITE STATUS REGISTER (WRSR)

This instruction lets the user choose a Block Protection

setting. The values of the other data bits incorporated

into WRSR can be 0 or 1, and are not stored in the

Status Register. WRSR will be ignored unless both the

following are true: a) WEN = 1, due to a prior WREN

instruction; and b) Hardware Write Protection is not

enabled. (See Table 4 for details). Except for the RDY

status, the values in the Status Register remain un-

changed until the moment when the write cycle is

complete and the register is updated. Once successfully

completed, WEN is reset for complete chip write protec-

tion. (See Figure 5 for timing).

READ DATA (READ)

This instruction begins with the op-code and the 8-bit

address, and causes the selected data byte to be

shifted out on SO. Following this first data byte, addi-

tional sequential bytes are output. If the data byte in the

highest address is output, the address rolls-over to the

lowest address in the array, and the output could loop

indefinitely. At any time, a rising CS signal completes

the operation. (See Figure 6 for timing).

WRITE DATA (WRITE)

The WRITE instruction begins with the op-code, the 8-bit

address of the first byte to be modified, and the first data

byte. Additional data bytes may be written sequentially

to the array after the first byte. Each WRITE instruction

can affect the contents of a 8 byte page, but no more.

The page begins at address XXXXX 000, and ends with

XXXXX 111. If the last byte of the page is input, the

address rolls over to the beginning of the same page.

More than 8 data bytes can be input during the same

instruction, but upon a completed write cycle, a page

would only contain the last 8 bytes.

The region of the array defined within Block Protection

cannot be modified as long as that block configuration is

selected. The region of the array outside the Block

Protection can only be modified if Write Enable (WEN) is

set to 1. Therefore, it may be necessary that a WREN

instruction occur prior to WRITE. In addition, if Hardware

Write Protection is enabled, the memory array cannot be

modified. Once Write is successfully completed, WEN

is reset for complete chip write protection. (See Figure 7

for timing).

Table 4. Write Protection

WP Hardware Write

Protection

0

Enabled

1

Not Enabled

1

Not Enabled

Note: X = Don't care bit.

WEN Inside Block Outside Block

X

Read-only

Read-only

0

Read-only

Read-only

1

Read-only

Unprotected

Status Register

Read-only

Read-only

Unprotected

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Preliminary Information Rev. 00B

12/23/05

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