ILC7080AIM527 Ver la hoja de datos (PDF) - Fairchild Semiconductor

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componentes Descripción

Fabricante

ILC7080AIM527

50/100mA SOT-23 CMOS RF LDO™ Regulators

Fairchild Semiconductor 

ILC7080/81

The layout of the LDO and its external components are also

based on some simple rules to minimize EMI and output

voltage ripple.

VBATT

+

DC/DC

Converter

GND

VOUT

CNOISE

5

4

ILC7080

0.01µF

COUT

4.7µF

L

O

SOT23-5

ESR<0.5Ω A

VIN

12 3

ON/OFF

D

CIN

1µF

Ground Plane

Ground Plane Ground Plane

Ground Plane

Figure 8. Recommended application circuit schematic

Figure 9. Recommended application circuit layout

(not drawn to scale).

Note: ground plane is bottom layer of PCB and connects to

top layer ground connections through vias.

Evaluation Board Parts List For Printed Circuit Board Shown Above

Label

U1

J1

CIN

CNOISE

COUT

Part Number

ILC7081AIM5-30

69190-405

GRM40 Y5V 105Z16

ECU-V1H103KBV

GRM42-6X5R475K10

Manufacturer

Fairchild Semi.

Berg

muRata

Panasonic

muRata

Description

100mA RF LDOTM regulator

Connector, four position header

Ceramic capacitor, 1µF,16V, SMT (size 0805)

Ceramic capacitor, 0.01µF,16V, SMT (size 0603)

Ceramic capacitor, 4.7µF,16V, SMT (size 1206)

Grounding Recommendations

1. Connect CIN between VIN of the ILC7080/81 and the “GROUND PLANE”.

2. Keep the ground side of COUT and CNOISE connected to the “LOCAL GROUND” and not directly to the “GROUND

PLANE”.

3. On multilayer boards use component side copper for grounding around the ILC7080/81 and connect back to a “GROUND

PLANE” using vias.

4. If using a DC-DC converter in your design, use a star grounding system with separate traces for the power ground and the

control signals. The star should radiate from where the power supply enters the PCB.

Layout Considerations

1. Place all RF LDO related components; ILC7080/81, input capacitor CIN, noise bypass capacitor CNOISE and output capac-

itor COUT as close together as possible.

2. Keep the output capacitor COUT as close to the ILC7080/81 as possible with very short traces to the VOUT and GND pins.

3. The traces for the related components; ILC7080/81, input capacitor CIN, noise bypass capacitor CNOISE and output capac-

itor COUT can be run with minimum trace widths close to the LDO.

4. Maintain a separate “LOCAL GROUND” remote from the “GROUND PLANE” to ensure a quiet ground near the LDO.

Figure 9 shows how this circuit can be translated into a PCB layout.

8

REV. 1.0.7 4/3/03

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