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IDT72401

CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT

Integrated Device Technology 

IDT72401, IDT72402, IDT72403, IDT72404

CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING CONDITIONS

(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)

Symbol

tSIH(1)

tSIL

tIDS

tIDH

tSOH(1)

tSOL

tMRW

tMRS

tSIR

tHIR

tSOR(4)

Parameters

Shift in HIGH Time

Shift in LOW TIme

Input Data Set-up

Input Data Hold Time

Shift Out HIGH Time

Shift Out LOW Time

Master Reset Pulse

Master Reset Pulse to SI

Data Set-up to IR

Data Hold from IR

Data Set-up to OR HIGH

Commercial

Military and Commercial

IDT72401L45 IDT72401L35 IDT72401L25 IDT72401L15 IDT72401L10

IDT72402L45 IDT72402L35 IDT72402L25 IDT72402L15 IDT72402L10

IDT72403L45 IDT72403L35 IDT72403L25 IDT72403L15 IDT72403L10

IDT72404L45 IDT72404L35 IDT72404L25 IDT72404L15 IDT72404L10

FIgure Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

2

9

—

9

—

11

—

11

—

11

—

ns

2

11

—

17

—

24

—

25

—

30

—

ns

2

0

—

0

—

0

—

0

—

0

— ns

2

13

—

15

—

20

—

30

—

40

—

ns

5

9

—

9

—

11

—

11

—

11

—

ns

5

11

—

17

—

24

—

25

—

25

—

ns

8

20

—

25

—

25

—

25

—

30

—

ns

8

10

—

10

—

10

—

25

—

35

—

ns

4

3

—

3

—

5

—

5

—

5

— ns

4

13

—

15

—

20

—

30

—

30

—

ns

7

0

—

0

—

0

—

0

—

0

— ns

2747 tbl 05

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)

Symbol

tIN

tIRL(1)

tIRH(1)

tOUT

tORL(1)

tORH(1)

tODH

tODS

Parameters

Shift In Rate

Shift In to Input Ready LOW

Shift In to Input Ready HIGH

Shift Out Rate

Shift Out to Output Ready LOW

Shift Out to Output Ready HIGH

Output Data Hold (Previous Word)

Output Data Shift (Next Word)

FIgure

Commercial

IDT72401L45

IDT72402L45

IDT72403L45

IDT72404L45

Min. Max.

2

—

45

2

—

18

2

—

18

5

—

45

5

—

18

5

—

19

5

5

—

5

—

19

IDT72401L35

IDT72402L35

IDT72403L35

IDT72404L35

Min. Max.

—

35

—

18

—

20

—

35

—

18

—

20

5

—

—

20

Military and Commercial

IDT72401L25

IDT72402L25

IDT72403L25

IDT72404L25

IDT72401L15

IDT72402L15

IDT72403L15

IDT72404L15

Min. Max. Min. Max.

—

25

—

15

—

21

—

35

—

28

—

40

—

25

—

15

—

19

—

35

—

34

—

40

5

—

5

—

—

34

—

40

IDT72401L10

IDT72402L10

IDT72403L10

IDT72404L10

Min. Max.

—

10

—

40

—

45

—

10

—

40

—

55

5

—

—

55

Unit

MHz

ns

ns

MHz

ns

ns

ns

ns

tPT

Data Throughput or "Fall-Through"

4, 7 —

30

—

34

—

40

—

65

—

65 ns

tMRORL

tMRIRH

Master Reset to OR LOW

Master Reset to IR HIGH

8

—

25

—

28

—

35

—

35

—

40 ns

8

—

25

—

28

—

35

—

35

—

40 ns

tMRQ

tOOE(3)

tHZOE(3,4)

tIPH(2,4)

tOPH(2,4)

Master Reset to Data Output LOW

Output Valid from OE LOW

Output High-Z from OE HIGH

Input Ready Pulse HIGH

Ouput Ready Pulse HIGH

8

—

20

—

20

—

25

—

35

—

40 ns

9

—

12

—

15

—

20

—

30

—

35 ns

9

—

12

—

12

—

15

—

25

—

30 ns

4

9

—

9

—

11

—

11

—

11

—

ns

7

9

—

9

—

11

—

11

—

11

—

ns

NOTES:

2747 tbl 06

1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding

and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor

supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended.

2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of

like speed grades.

3. IDT72403 and IDT72404 only.

4. Guaranteed by design but not currently tested.

5.01

3

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