IDT72401L35PGB(2012) Ver la hoja de datos (PDF) - Integrated Device Technology

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componentes Descripción

Fabricante

IDT72401L35PGB
(Rev.:2012)

CMOS PARALLEL FIFO 64 x 4

Integrated Device Technology 

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

(2)

SO

SI

IR (1)

(3)

tPT

(4)

tSIR

tIPH

tHIR

INPUT DATA

STABLE DATA

NOTES:

1. FIFO is initially full.

2. SO pulse is applied.

3. SI is held HIGH.

4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.

5. The write pointer is incremented. SI should not go LOW until (tPT + tIPH).

Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH

(5)

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tSOH

1/fOUT

tSOL

SO

1/fOUT

(2)

tORH

OR

OUTPUT DATA

(1)

tODH

A-DATA

tODS

tORL

B-DATA

NOTES:

1. This data is loaded consecutively A, B, C.

2. Data is shifted out when SO makes a HIGH to LOW transition.

Figure 5. Output TIming

C-DATA

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SO(7)

(2)

(4)

(1)

(5)

OR

(3)

OUTPUT DATA

A- DATA

A or B

NOTES:

1. OR HIGH indicates that data is available and a SO pulse may be applied.

2. SO goes HIGH causing the next step.

3. OR goes LOW.

4. The read pointer is incremented.

5. OR goes HIGH indicating that new data (B) is now available at the FIFO outputs.

6. If the FIFO has only one word loaded (A DATA) then OR stays LOW and the A DATA remains unchanged at the outputs.

7. SO pulses applied when OR is LOW will be ignored.

Figure 6. The Mechanism of Shifting Data Out of the FIFO

6

(6)

B- DATA

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JUNE 29, 2012

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