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Número de pieza

componentes Descripción

Fabricante

IDT72401
(Rev.:2005)

CMOS PARALLEL FIFO 64 x 4 and 64 x 5

Integrated Device Technology

IDT72401 Datasheet PDF : 9 Pages

1 2 3 4 5 6 7 8 9

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

D3 MR Q3

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

SHIFT OUT

COMPOSITE

INPUT

READY

D3 MR Q3

COMPOSITE

OUTPUT

READY

SHIFT IN

D3 MR Q3

2747 drw 15

NOTES:

1. When the memory is empty, the last word will remain on the outputs until the MR is strobed or a new data word falls through to the output. However, OR will remain LOW,

indicating data at the output is not valid.

2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until the new data

has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.

3. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will go HIGH for one

internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will line up behind the

first word and will not appear on the outputs until SO has been brought LOW.

4. When the MR is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the MR goes HIGH, the data on the inputs will be

written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the MR is ended, IR will go HIGH, but the data in the inputs will not

enter the memory until SI goes HIGH.

5. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and OR flags. This is due to the

variation of delays of the FIFOs.

Figure 11. 192 x 12 Depth and Width Expansion

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