IDT72401(2005) Ver la hoja de datos (PDF) - Integrated Device Technology

Número de pieza

componentes Descripción

Fabricante

IDT72401
(Rev.:2005)

CMOS PARALLEL FIFO 64 x 4 and 64 x 5

Integrated Device Technology 

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

SI

SO

OR (1)

DATA OUTPUT

NOTE:

1. FIFO initially empty.

tPT

tSOR

Figure 7. tPT and tOPH Specification

MR

IR (1)

(1)

OR

SI

DATA OUTPUT

NOTE:

1. Worst case, FIFO initially full.

tMRW

tMRIRH

tMRORL

tMRQ

tMRS

Figure 8. Master Reset Timing

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

tOPH

DATA VALID

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OE

tHZOE

tOOE

DATA OUT

NOTE:

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1. High-Z transitions are referenced to the steady-state VOH –500mV and VOL +500mV levels on the output. tHZOE is tested with 5pF load capacitance instead of 30pF as

shown in Figure 1.

Figure 9. Output Enable Timing, IDT72403 Only

SHIFT IN

INPUT READY

DATA IN

SI

OR

IR

SO

D0

Q0

D1

Q1

D2

Q2

D3 MR Q3

SI

OR

IR

SO

D0

Q0

D1

Q1

D2

Q2

D3 MR Q3

OUTPUT READY

SHIFT OUT

DATA OUT

MR

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NOTE:

1. FIFOs can be easily cascaded to any desired path. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices.

Figure 10. 128 x 4 Depth Expansion

7

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