IDT72401(2005) Ver la hoja de datos (PDF) - Integrated Device Technology
Número de pieza
componentes Descripción
Fabricante
IDT72401 Datasheet PDF : 9 Pages
| |||
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
MILITARY AND COMMERCIAL
TEMPERATURE RANGES
ALL INPUT PULSES:
3.0V
GND
90%
10%
<3ns
90%
10%
<3ns
2747 drw 04
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
NOTE:
1. Characterized values, not currently tested.
Max. Unit
5
pF
7
pF
5V
1.1KΩ
560Ω
OUTPUT
30pF*
2747 drw 05
or equivalent circuit
Figure 1. AC Test Load
*Including scope and jig
SIGNAL DESCRIPTIONS
INPUTS:
DATA INPUT (D0-3)
Data input lines. The IDT72401 and IDT72403 have a 4-bit data input.
CONTROLS:
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When SI is HIGH, data
can be written to the FIFO via the D0-3 lines.
SHIFT OUT (SO)
Shift Out controls the output of data of the FIFO. When SO is HIGH, data can
be read from the FIFO via the Data Output (Q0-3) lines.
MASTER RESET (MR)
Master Reset clears the FIFO of any data stored within. Upon power up, the
FIFO should be cleared with a MR. MR is active LOW.
INPUT READY (IR)
When Input Ready is HIGH, the FIFO is ready for new input data to be written
to it. When IR is LOW the FIFO is unavailable for new input data. IR is also used
to cascade many FlFOs together, as shown in Figures 10 and 11.
OUTPUT READY (OR)
When Output Ready is HIGH, the output (Q0-3) contains valid data. When
OR is LOW, the FIFO is unavailable for new output data. OR is also used to
cascade many FlFOs together, as shown in Figures 10 and 11.
OUTPUT ENABLE (OE) (IDT72403 ONLY)
Output enable is used to read FIFO data onto a bus. OE is active LOW.
OUTPUTS:
DATA OUTPUT (Q0-3)
Data Output lines. The IDT72401 and IDT72403 have a 4-bit data output.
4
Share Link: 