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ICS1893CY-10LF

3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

Integrated Circuit Systems 

ICS1893CY-10 Data Sheet - Release

Table of Contents

Table of Contents

Section

7.11

7.11.1

7.11.2

7.11.3

7.11.4

7.11.5

7.11.6

7.11.7

7.11.8

7.11.9

7.12

7.12.1

7.12.2

7.12.3

7.12.4

7.12.5

7.12.6

7.12.7

7.12.8

7.12.9

7.12.10

7.12.11

7.12.12

7.12.13

7.12.14

7.13

7.13.1

7.13.2

7.13.3

7.13.4

7.13.5

7.13.6

7.13.7

7.13.8

7.13.9

Title

Page

Register 16: Extended Control Register ................................................................84

Command Override Write Enable (bit 16.15) .........................................................85

ICS Reserved (bits 16.14:11) .................................................................................85

PHY Address (bits 16.10:6) ...................................................................................85

Stream Cipher Scrambler Test Mode (bit 16.5) .....................................................85

ICS Reserved (bit 16.4) .........................................................................................85

NRZ/NRZI Encoding (bit 16.3) ...............................................................................85

Invalid Error Code Test (bit 16.2) ...........................................................................86

ICS Reserved (bit 16.1) .........................................................................................86

Stream Cipher Disable (bit 16.0) ............................................................................86

Register 17: Quick Poll Detailed Status Register ...................................................87

Data Rate (bit 17.15) ..............................................................................................88

Duplex (bit 17.14) ...................................................................................................88

Auto-Negotiation Progress Monitor (bits 17.13:11) ................................................88

100Base-TX Receive Signal Lost (bit 17.10) .........................................................89

100Base PLL Lock Error (bit 17.9) .........................................................................89

False Carrier (bit 17.8) ...........................................................................................90

Invalid Symbol (bit 17.7) ........................................................................................90

Halt Symbol (bit 17.6) ............................................................................................90

Premature End (bit 17.5) ........................................................................................91

Auto-Negotiation Complete (bit 17.4) .....................................................................91

100Base-TX Signal Detect (bit 17.3) .....................................................................91

Jabber Detect (bit 17.2) .........................................................................................91

Remote Fault (bit 17.1) ..........................................................................................91

Link Status (bit 17.0) ..............................................................................................91

Register 18: 10Base-T Operations Register ..........................................................92

Remote Jabber Detect (bit 18.15) ..........................................................................92

Polarity Reversed (bit 18.14) .................................................................................93

ICS Reserved (bits 18.13:6) ...................................................................................93

Jabber Inhibit (bit 18.5) ..........................................................................................93

ICS Reserved (bit 18.4) .........................................................................................93

Auto Polarity Inhibit (bit 18.3) .................................................................................93

SQE Test Inhibit (bit 18.2) ......................................................................................94

Link Loss Inhibit (bit 18.1) ......................................................................................94

Squelch Inhibit (bit 18.0) ........................................................................................94

ICS1893CY-10 Rev 1/07

Copyright © 2007, Integrated Device Technology, Inc.

All rights reserved.

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