ICS1893CY-10LF Ver la hoja de datos (PDF) - Integrated Circuit Systems

Número de pieza

componentes Descripción

Fabricante

ICS1893CY-10LF

3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

Integrated Circuit Systems 

Integrated Device Technology, Inc.

ICS1893CY-10

Document Type: Data Sheet

Document Stage: Preliminary Release

3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

General

The ICS1893CY-10 is a low-power, physical-layer device

(PHY) that supports the ISO/IEC 10Base-T and 100Base-TX

Carrier-Sense Multiple Access/Collision Detection

(CSMA/CD) Ethernet standards. The ICS1893CY-10

supports managed or unmanaged node, repeater, and

switch applications.

The ICS1893CY-10 is intended for MII, Node applications

that require the Auto-MIDIX feature that automatically

corrects crossover errors in plant wiring.

The ICS1893CY-10 incorporates digital signal processing

(DSP) in its Physical Medium Dependent (PMD) sublayer.

As a result, it can transmit and receive data on unshielded

twisted-pair (UTP) category 5 cables with attenuation in

excess of 24 dB at 100 MHz. With this ICS-patented

technology, the ICS1893CY-10 can virtually eliminate errors

from killer packets.

The ICS1893CY-10 provides a Serial Management Interface

for exchanging command and status information with a

Station Management (STA) entity.

The ICS1893CY-10 Media Dependent Interface (MDI) can

be configured to provide either half- or full-duplex operation

at data rates of 10 MHz or 100 MHz. The MDI configuration

can be established manually (with input pins or control

register settings) or automatically (using the

Auto-Negotiation features). When the ICS1893CY-10

Auto-Negotiation sublayer is enabled, it exchanges

technology capability data with its remote link partner and

automatically selects the highest-performance operating

mode they have in common.

Features

• Supports category 5 cables with attenuation in excess of

24 dB at 100 MHz

• Fully integrated, DSP-based PMD includes:

– Adaptive equalization and baseline wander correction

– Transmit wave shaping and stream cipher scrambler

– MLT-3 encoder and NRZ/NRZI encoder

• Low-power, 0.35-micron CMOS (typically 400 mW)

• Power-down mode typically 21mW

• Single 3.3-V power supply.

• Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard

• 10Base-T and 100Base-TX IEEE 802.3 compliant

• Highly configurable design supports:

– Node, repeater, and switch applications

– Managed and unmanaged applications

– 10M or 100M half- and full-duplex modes

– Parallel detection

– Auto-negotiation, with Next Page capabilities

– Auto-MDI/MDIX crossover correction

• MAC/Repeater Interface can be configured as:

– 10M or 100M Media Independent Interface

– 100M Symbol Interface (bypasses the PCS)

– 10M 7-wire Serial Interface

• Clock and crystal supported

• Small Footprint 64-pin Thin Quad Flat Pack (TQFP)

• Available in Industrial Temperature and Lead-Free

ICS1893CY-10 Block Diagram

10/100 MII or

Alternate

MAC/Repeater

Interface

Interface

MUX

PCS

• Frame

• CRS/COL

Detection

• Parallel to Serial

• 4B/5B

MII Serial

Management

Interface

MII

Extended

Register

Set

Low-Jitter

Clock

Synthesizer

Clock

100Base-T

PMA

• Clock Recovery

• Link Monitor

• Signal Detection

• Error Detection

10Base-T

TP_PMD

• MLT-3

• Stream Cipher

• Adaptive Equalizer

• Baseline Wander

Correction

Configuration

and Status

Integrated

Switch

Auto-

Negotiation

Twisted-

Pair

Interface to

Magnetics

Modules and

RJ45

Connector

Power

LEDs and PHY

Address

ICS1893CY-10

Rev 1/07

IDT reserves the right to make changes in the device data identified in

this publication without further notice. IDT advises its customers to

obtain the latest version of all device data to verify that any information

being relied upon by the customer is current and accurate.

Share Link: