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GS72108AJ-15I

256K x 8 2Mb Asynchronous SRAM

Giga Semiconductor 

AC Characteristics

GS72108ATP/J

Read Cycle

Parameter

-7

-8

-10

-12

Symbol

Unit

Min Max Min Max Min Max Min Max

Read cycle time

tRC

7

—

8

—

10 — 12 —

ns

Address access time

tAA

—

7

—

8

— 10 — 12

ns

Chip enable access time (CE)

tAC

—

7

—

8

— 10 — 12

ns

Byte enable access time (UB, LB)

tAB

—

3

—

3.5

—

4

—

5

ns

Output enable to output valid (OE)

tOE

—

3

—

3.5

—

4

—

5

ns

Output hold from address change

tOH

3

—

3

—

3

—

3

—

ns

Chip enable to output in low Z (CE)

tLZ*

3

—

3

—

3

—

3

—

ns

Output enable to output in low Z (OE)

tOLZ*

0

—

0

—

0

—

0

—

ns

Byte enable to output in low Z (UB, LB) tBLZ*

0

—

0

—

0

—

0

—

ns

Chip disable to output in High Z (CE)

tHZ*

—

3.5

—

4

—

5

—

6

ns

Output disable to output in High Z (OE) tOHZ*

—

3

—

3.5

—

4

—

5

ns

* These parameters are sampled and are not 100% tested.

Read Cycle 1: CE = OE = VIL, WE = VIH

Address

Data Out

tOH

Previous Data

tRC

tAA

Data valid

Rev: 1.04a 10/2002

6/12

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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