3130 Ver la hoja de datos (PDF) - Harris Semiconductor
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3130 Datasheet PDF : 15 Pages
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CA3130, CA3130A
metal can package also contributes an increment of leakage
current, there are useful compensating factors. Because the
gate-protection network functions as if it is connected to Ter-
minal 4 potential, and the Metal Can case of the CA3130 is
also internally tied to Terminal 4, input Terminal 3 is essen-
tially “guarded” from spurious leakage currents.
10
TA = 25oC
In applications requiring the lowest practical input current
and incremental increases in current because of “warm-up”
effects, it is suggested that an appropriate heat sink be used
with the CA3130. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heat-
sinking can also very markedly reduce and stabilize input
current variations.
7.5
15V
V+ TO
5V
7
5
2
PA
CA3130
6
3
2.5
8
VIN
4
0V
TO
-10V
0
V-
-1 0 1 2 3 4 5 6 7
INPUT CURRENT (pA)
FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE
Offset Nulling
Offset-voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
potentiometer’s total range.
Input-Current Variation with Temperature
The input current of the CA3130 Series circuits is typically
5pA at 25oC. The major portion of this input current is due to
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor-junction device, including
op amps with a junction-FET input stage, the leakage current
approximately doubles for every 10oC increase in tempera-
ture. Figure 4 provides data on the typical variation of input
bias current as a function of temperature in the CA3130.
4000
1000
VS = ±7.5V
100
Input Offset Voltage (VIO) Variation with DC Bias and
Device Operating Life
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magni-
tude of the change is increased at high temperatures. Users
of the CA3130 should be alert to the possible impacts of this
effect if the application of the device involves extended oper-
ation at high temperatures with a significant differential DC
bias voltage applied across Terminals 2 and 3. Figure 5
shows typical data pertinent to shifts in offset voltage
encountered with CA3130 devices (metal can package) dur-
ing life testing. At lower temperatures (metal can and plas-
tic), for example at 85oC, this change in voltage is
considerably less. In typical linear applications where the dif-
ferential voltage is small and symmetrical, these incremental
changes are of about the same magnitude as those encoun-
tered in an operational amplifier employing a bipolar transis-
tor input stage. The 2VDC differential voltage example
represents conditions when the amplifier output stage is
“toggled”, e.g., as in comparator applications.
o
7
TA = 125oC FOR TO-5 PACKAGES
6
DIFFERENTIAL DC VOLTAGE
5
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
4
3
2
DIFFERENTIAL DC VOLTAGE
1
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2
0
0 500 1000 1500 2000 2500 3000 3500 4000
TIME (HOURS)
FIGURE 5. TYPICAL INCREMENTAL OFFSET-VOLTAGE
SHIFT vs OPERATING LIFE
10
1
-80 -60 -40 -20 0 20 40 60 80
TEMPERATURE (oC)
100 120 140
FIGURE 4. INPUT CURRENT vs TEMPERATURE
3-69
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