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GT28F400B3B150

SMART 3 ADVANCED BOOT BLOCK WORD-WIDE 4-MBIT (256K X 16), 8-MBIT (512K X 16), 16-MBIT (1024K X 16) FLASH MEMORY FAMILY

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

1.0 INTRODUCTION

This preliminary datasheet contains the

specifications for the Advanced Boot Block flash

memory family, which is optimized for low power,

portable systems. This family of products features

1.8V–2.2V or 2.7V–3.6V I/Os and a low VCC/VPP

operating range of 2.7V–3.6V for read and

program/erase operations. In addition this family is

capable of fast programming at 12V. Throughout

this document, the term “2.7V” refers to the full

voltage range 2.7V–3.6V (except where noted

otherwise) and “VPP = 12V” refers to 12V ±5%.

Section 1 and 2 provides an overview of the flash

memory family including applications, pinouts and

pin descriptions. Section 3 describes the memory

organization and operation for these products.

Finally, Sections 4, 5, 6 and 7 contain the

operating specifications.

1.1 Smart 3 Advanced Boot Block

Flash Memory Enhancements

The new 4-Mbit, 8-Mbit, and 16-Mbit Smart 3

Advanced Boot Block flash memory provides a

convenient upgrade from and/or compatibility to

previous 4-Mbit and 8-Mbit Boot Block products.

The Smart 3 product functions are similar to lower

density products in both command sets and

operation, providing similar pinouts to ease density

upgrades.

The Smart 3 Advanced Boot Block flash memory

features

• Enhanced blocking for easy segmentation of

code and data or additional design flexibility

• Program Suspend command which permits

program suspend to read

• WP# pin to lock and unlock the upper two (or

lower two, depending on location) 4-Kword

blocks

• VCCQ input for 1.8V–2.2V on all I/Os. See

Figure 1-4 for pinout diagrams and VCCQ

location

• Maximum program time specification for

improved data storage.

Table 1. Smart 3 Advanced Boot Block Feature Summary

Feature

28F160B3

VCC Read Voltage

2.7V– 3.6V

VCCQ I/O Voltage

1.8V–2.2V or 2.7V– 3.6V

VPP Program/Erase Voltage 2.7V– 3.6V or 11.4V– 12.6V

Bus Width

16 bit

Speed

120 ns

Memory Arrangement

256-Kbit x 16 (4-Mbit), 512-Kbit x 16 (8-Mbit),

1024-Kbit x 16 (16-Mbit)

Blocking (top or bottom)

Eight 4-Kword parameter blocks (4/8/16) &

Seven 32-Kword blocks (4-Mbit)

Fifteen 32-Kword blocks (8-Mbit)

Thirty-one 32-Kword main blocks (16-Mbit)

Locking

WP# locks/unlocks parameter blocks

All other blocks protected using VPP switch

Operating Temperature

Extended: –40°C to +85°C

Program/Erase Cycling

10,000 cycles

Packages

48-Lead TSOP, 48-Ball µBGA* CSP

Reference

Table 9, Table 12

Table 9, Table 12

Table 9, Table 12

Table 2

Table 15

Section 2.2

Figures 5 and 6

Section 3.3

Table 8

Table 9, Table 12

Table 9, Table 12

Figures 1, 2, 3,

and 4

PRELIMINARY

5

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