EN29F512 Ver la hoja de datos (PDF) - Eon Silicon Solution Inc.

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EN29F512

512 Kbit (64K x 8-bit) 5V Flash Memory

Eon Silicon Solution Inc. 

EN29F512

512 Kbit (64K x 8-bit) 5V Flash Memory

EN29F512

FEATURES

• 5.0V operation for read/write/erase

operations

• Fast Read Access Time

- 45ns, 55ns, 70ns, and 90ns

• Sector Architecture:

- 4 uniform sectors of 16Kbytes each

- Supports full chip erase

- Individual sector erase supported

- Sector protection:

Hardware locking of sectors to prevent

program or erase operations within

individual sectors

• High performance program/erase speed

- Byte program time: 7µs typical

- Sector erase time: 300ms typical

- Chip erase time: 1.5s typical

• Low Standby Current

- 1µA CMOS standby current-typical

- 1mA TTL standby current

• Low Power Active Current

- 12mA typical active read current

- 30mA program/erase current

• JEDEC Standard program and erase

commands

• JEDEC standard DATA polling and toggle

bits feature

• Single Sector and Chip Erase

• Sector Unprotect Mode

• Embedded Erase and Program Algorithms

• Erase Suspend / Resume modes:

Read and program another Sector during

Erase Suspend Mode

• 0.23 µm triple-metal double-poly

triple-well CMOS Flash Technology

• Low Vcc write inhibit < 3.2V

• 100K endurance cycle

• Package Options

- 32-pin PDIP

- 32-pin PLCC

- 32-pin 8mm x 20mm TSOP (Type 1)

- 32-pin 8mm x 14mm TSOP (Type 1)

• Commercial and Industrial Temperature

Ranges

GENERAL DESCRIPTION

The EN29F512 is a 512-Kbit, electrically erasable, read/write non-volatile flash memory. Organized

into 64K bytes with 8 bits per byte, the 512K of memory is arranged in four uniform sectors of

16Kbytes each. Any byte can be programmed typically in 7µs. The EN29F512 features 5.0V

voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT

states in high-performance microprocessor systems.

The EN29F512 has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable ( W E )

controls, which eliminate bus contention issues. This device is designed to allow either single

Sector or full chip erase operation, where each Sector can be individually protected against

program/erase operations or temporarily unprotected to erase or program. The device can sustain a

minimum of 100K program/erase cycles on each Sector.

This Data Sheet may be revised by subsequent versions 1

or modifications due to changes in technical specifications.

©2003 Eon Silicon Solution, Inc., www.essi.com.tw

Rev. A, Issue Date: 2003/10/20

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