CY7C68001(2004) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C68001
(Rev.:2004)

High-Speed USB Interface Device

Cypress Semiconductor 

FO R

FO R

• Command data write of upper nibble of the Low Byte of

Register Address (0x08)

• Command data write of lower nibble of the Low Byte of

Register Address (0x03)

(2) Send High Byte of the Register (0xE6)

• Command address write of address 0x3B

• Command data write of upper nibble of the High Byte of

Register Address (0x0E)

• Command data write of lower nibble of the High Byte of

Register Address (0x06)

(3) Get the actual value from the TOGCTL register (0x16)

• Command address READ of 0x3C

6.0 Pin Assignments

6.1 56-pin SSOP

1 FD13

FD12 56

2 FD14

FD11 55

3 FD15

FD10 54

4 GND

FD9 53

5 NC

FD8 52

6 VCC

*WAKEUP 51

7 GND

VCC 50

8 *SLRD

RESET# 49

9 *SLWR

GND 48

10 AVCC

*FLAGD/CS# 47

11 XTALOUT

*PKTEND 46

12 XTALIN

FIFOADR1 45

13 AGND

FIFOADR0 44

14 VCC

FIFOADR2 43

15 DPLUS

*SLOE 42

16 DMINUS

INT# 41

17 GND

READY 40

18 VCC

VCC 39

19 GND

*FLAGC 38

20 *IFCLK

*FLAGB 37

21 RESERVED

*FLAGA 36

22 SCL

23 SDA

24 VCC

CY7C68001 GND 35

56-pin SSOP VCC 34

GND 33

25 FD0

FD7 32

26 FD1

FD6 31

27 FD2

FD5 30

28 FD3

FD4 29

Note:

7. A * denotes programmable polarity.

Figure 6-1. CY7C68001 56-pin SSOP Pin Assignment[7]

CY7C68001

Document #: 38-08013 Rev. *E

Page 10 of 42

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