CY7C1399B Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1399B Datasheet PDF : 10 Pages
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CY7C1399B
Switching Characteristics Over the Operating Range[6]
1399B-10
1399B-12
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
Write Cycle[9, 10]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[7, 8]
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
10
12
ns
10
12
ns
3
3
ns
10
12
ns
5
5
ns
0
0
ns
5
5
ns
3
3
ns
5
6
ns
0
0
ns
10
12
ns
tWC
Write Cycle Time
10
12
ns
tSCE
CE LOW to Write End
8
8
ns
tAW
Address Set-Up to Write End
7
8
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
7
8
ns
tSD
Data Set-Up to Write End
5
7
ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High Z[9]
WE HIGH to Low Z[7]
0
0
ns
7
7
ns
3
3
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and capacitance CL = 30 pF.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05071 Rev. *C
Page 4 of 10
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