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CXD2300Q Ver la hoja de datos (PDF) - Sony Semiconductor

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componentes Descripción
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CXD2300Q Datasheet PDF : 14 Pages
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CXD2300Q
DC characteristics
Item
Supply current
Reference pin current
Analog input capacitance
Reference resistance
(VRT to VRB)
Self-bias
Digital input voltage
Digital input current
Digital output current
Symbol
IDD
IREF
CIN
(Fc = 18MSPS, VDD = 3.3 V, VRB = 0 V, VRT = 1.5 V, Ta = 25 °C)
Conditions
Fc = 18MSPS
NTSC ramp wave input
VIN = 0.75 V + 0.07 Vrms
Min. Typ. Max. Unit
5.5 10 mA
3.3 4.6 6.6 mA
8
pF
RREF
230 330 440
VRB1
VRT1 – VRB1
Shorts VRB and VRBS
Shorts VRT and VRTS
0.33 0.36 0.39
V
1.30 1.39 1.48
VIH
VDD = 3.14 to 3.6 V
VIL
Ta = –40 to +85 °C
2.5
V
0.5
IIH
VIH = VDD
VDD = max
IIL
VIL = 0 V
5
µA
5
IOH
OE = VSS VOH = VDD – 0.5 V –1.0
mA
IOL
VDD = min VOL = 0.4 V
3.3
IOZH
IOZL
OE = VDD
VDD = max
VOH = VDD
VOL = 0 V
16
µA
16
Timing
(Fc = 18MSPS, VDD = 3. 3V, VRB = 0 V, VRT = 1.5 V, Ta = 25 °C)
Item
Symbol
Conditions
Min. Typ. Max. Unit
Output data delay
TDL
With TTL 1 gate and 10pF load
VDD = 3.14 to 3.6 V
8
Ta = –40 to +85 °C
18 30 ns
Tri-state output
enable time
RL = 1 k, CL = 20 pF
tPZH
OE = 3 V 0 V
tPZL
VDD = 3.14 to 3.6 V
Ta = –40 to +85°C
6
12 25 ns
Tri-state output
disable time
RL = 1 k, CL = 20 pF
tPHZ
OE = 0 V 3 V
tPLZ
VDD = 3.14 to 3.6 V
Ta = –40 to +85 °C
4
7.5 16 ns
Clamp pulse width1
tcpw
Fc = 14.3MSPS, CIN = 10 µF
for NTSC wave
1.75 2.75 3.75 µs
1 The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75 kHz
for NTSC) for other processing systems to equal the values for NTSC.
—8—

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