NE568AD Ver la hoja de datos (PDF) - Philips Electronics
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NE568AD Datasheet PDF : 9 Pages
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Philips Semiconductors
150MHz phase-locked loop
Product specification
NE/SA568A
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
VCC
TJ
TSTG
PDMAX
θJA
Supply voltage
Junction temperature
Storage temperature range
Maximum power dissipation
Thermal resistance
ELECTRICAL CHARACTERISTICS
The elctrical characteristics listed below are actual tests (unless
otherwise stated) performed on each device with an automatic IC
tester prior to shipment. Performance of the device in automated
test set-up is not necessarily optimum. The NE568A is
RATING
6
+150
-65 to +150
400
80
UNITS
V
°C
°C
mW
°C/W
layout-sensitive. Evaluation of performance for correlation to the
data sheet should be done with the circuit and layout of Figures 3, 4,
and 5 with the evaluation unit soldered in place. (Do not use a
socket!)
DC ELECTRICAL CHARACTERISTICS
VCC = 5V; TA = 25°C; fO = 70MHz, Test Circuit Figure 3, fIN = -20dBm, R4 = 3.9kΩ, unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
NE/SA568A
MIN
TYP
VCC
Supply voltage
ICC
Supply current
4.5
5
54
MAX
5.5
70
UNITS
V
mA
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
NE/SA568A
UNITS
fOSC
Maximum oscillator operating frequency3
Input signal level
MIN
150
50
–201
TYP
MAX
2000
+10
MHz
mVP-P
dBm
BW
Demodulated bandwidth
Non-linearity5
Lock range2
Capture range2
TC of fO
RIN
Input resistance4
Output impedance
Demodulated VOUT
Dev = ±20%, Input = -20dBm
Input = -20dBm
±25
Input = -20dBm
±20
Figure 3
1
Dev = ±20% of fO measured at
Pin 14
0.40
fO/7
1.0
±35
±30
100
6
0.52
MHz
4.0
%
% of fO
% of fO
ppm/°C
kΩ
Ω
VP-P
AM rejection
fO
Distribution6
fO
Drift with supply
VIN = -20dBm (30% AM)
referred to ±20% deviation
Centered at 70MHz, R2 =
1.2kΩ, C2 = 16pF, R4 = 3.9kΩ
-15
(C2 + CSTRAY = 20pF)
4.5V to 5.5V
50
dB
0
+15
%
2
%/V
NOTE:
1. Signal level to assure all published parameters. Device will continue to function at lower levels with varying performance.
2. Limits are set symmetrical to fO. Actual characteristics may have asymmetry beyond the specified limits.
3. Not 100% tested, but guaranteed by design.
4. Input impedance depends on package and layout capacitances. See Figures 6 and 5.
5. Linearity is tested with incremental changes in inupt frequency and measurement of the DC output voltage at Pin 14 (VOUT). Non-linearity is
then calculated from a straight line over the deviation range specified.
6. Free-running frequency is measured as feedthrough to Pin 14 (VOUT) with no input signal applied.
1996 Feb 1
2
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