AT27LV256A-12JC Ver la hoja de datos (PDF) - Atmel Corporation
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AT27LV256A-12JC Datasheet PDF : 12 Pages
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AT27LV256A
Rapid Programming Algorithm
A 100 µs CE pulse width is used to program. The address
is set to the first location. VCC is raised to 6.5V and VPP is
raised to 13.0V. Each address is first programmed with one
100 µs CE pulse without verification. Then a verification /
reprogramming loop is executed for each address. In the
event a byte fails to pass verification, up to 10 successive
100 µs pulses are applied with a verification after each
pulse. If the byte fails to verify after 10 pulses have been
applied, the part is considered failed. After the byte verifies
properly, the next address is selected until all have been
checked. VPP is then lowered to 5.0V and VCC to 5.0V. All
bytes are read again and compared with the original data to
determine if the device passes or fails.
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