AS8S128K32P-15/883C Ver la hoja de datos (PDF) - Austin Semiconductor
Número de pieza
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Fabricante
AS8S128K32P-15/883C Datasheet PDF : 12 Pages
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Austin Semiconductor, Inc.
SRAM
AS8S128K32
NOTES
1. All voltages referenced to VSS (GND).
2. -3v for pulse width <20ns.
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
open, and f=
1
tRC(MIN)
HZ.
4. This parameter is sampled.
5. Test conditions as specified with output loading as
shown in Fig. 1 unless otherwise noted.
6. tHZCE, tHZOE and tHZWE are specified with CL= 5pF
as in Fig. 2. Transition is measured +/- 200 mV
typical from steady state coltage, allowing for actual
tester RC time constant.
7. At any given temperature and voltage condition,
tHZCE, is less than tLZCE, and tHZWE is less than tLZWE.
8. ?W/E is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and output
enable are held in their active state.
10. Address valid prior to or coincident with latest occurring
chip enable.
11. t = READ cycle time.
RC
12. Chip enable (?C/E) and write enable (?W/E) can initiate and
terminate a WRITE cycle.
13. 32 bit operation
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
VCC for Retention Data
CONDITIONS
SYMBOL MIN
VDR
2
MAX
--
CE\ > VCC - 0.2V VCC = 2.0V ICCDR
--
6
Data Retention Current
VIN > VCC - 0.2V
VCC = 3V
ICCDR
--
11.6
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
0
--
tR
tRC
UNITS
V
mA
mA
NOTES
ns
4
ns
4, 11
Vcc
VIH
CE\
VIL
LOW VCC DATA RETENTION WAVEFORM
tCDR
DATA RETENTION MODE
VDR >2V
4.5V
4.5V
tR
VDR
AS8S128K32
Rev. 4.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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