AS7C1024A-10STC Ver la hoja de datos (PDF) - Alliance Semiconductor

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AS7C1024A-10STC

5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)

Alliance Semiconductor 

AS7C1024A

AS7C31024A

®

Write cycle (over the operating range) 

-10

-12

-15

-20

Parameter

Symbol Min Max Min Max Min Max Min Max Unit

Write cycle time

tWC 10 – 12 – 15 – 20 –

ns

Chip enable (CE1) to write end

tCW1

8

– 10 – 12 – 12 –

ns

Chip enable (CE2) to write end

tCW2

8

– 10 – 12 – 12 –

ns

Address setup to write end

tAW

8 – 9 – 10 – 12 –

ns

Address setup time

tAS

0 – 0–0– 0 –

ns

Write pulse width

tWP

7 – 8 – 9 – 12 –

ns

Write recovery time

tWR

0 – 0–0– 0 –

ns

Address hold from end of write

tAH

0

–

0–0–

0

–

ns

Data valid to write end

tDW

5 – 6 – 8 – 10 –

ns

Data hold time

tDH

0 – 0–0– 0 –

ns

Write enable to output in high Z tWZ

– 6 –6–6 – 8

ns

Output active from write end

tOW

1

–

1–

1

–

2

–

ns

Write waveform 1 (WE controlled)

tWC

tAW

Address

tWP

WE

tAS

DIN

tWZ

DOUT

tWR

tAH

tDW

tDH

Data valid

tOW

Notes

12

12

12

4, 5

4, 5

4, 5

Write waveform 2 (CE1 and CE2 controlled)

tWC

tAW

Address

CE1

CE2

WE

DIN

DOUT

tAS

tCW1, tCW2

tWP

tWZ

tDW

Data valid

tAH

tWR

tDH

9/26/02; 0.9.9

Alliance Semiconductor

P. 5 of 9

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