APL5912 Ver la hoja de datos (PDF) - Anpec Electronics
Número de pieza
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APL5912 Datasheet PDF : 20 Pages
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APL5912
Pin Description
PIN
NO.
NAME
FUNCTION
1
GND
Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
Connecting this pin to an external resistor divider receives the feedback voltage of the
regulator. The output voltage set by the resistor divider is determined by :
2
FB
VOUT
=
0.8 ⋅ 1+
R1
R2
where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB to
GND. A bypass capacitor may be connected with R1 in parallel to improve load transient
response.
Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary
3,4
VOUT
to connect a output capacitor with this pin for closed-loop compensation and improve transient
responses.
Main supply input pins for power conversions. The Exposed Pad provides a very low
5
VIN
impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin
(Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for
Power-On-Reset purpose.
Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply
6
VCNTL voltage provides the bias for the control circuitry. The voltage at this pin is monitored for
Power-On-Reset purpose.
Power-OK signal output pin. This pin is an open-drain output used to indicate status of output
7
POK
voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above
the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is
not OK.
Enable control pin. Pulling and holding this pin below 0.3V shuts down the output. When
8
EN
re-enabled, the IC undergoes a new soft-start cycle. When leave this pin open, an internal
current source 10µA pulls this pin up to VCNTL voltage, enabling the regulator.
Main supply input pins for power conversions. The Exposed Pad provides a very low
-
Exposed Pad
impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin
(Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for
Power-On-Reset purpose.
Block Diagram
EN
VCNTL VIN
UV
0.4V
Soft-Start
and
Control Logic
Power-
On-Reset
Thermal
Limit
VREF
0.8V
EAMP
FB
POK
90%
VREF
Delay
Current
Limit
POK
VOUT
GND
Copyright © ANPEC Electronics Corp.
10
Rev. A.10 - Oct., 2009
www.anpec.com.tw
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