AL1213A Ver la hoja de datos (PDF) - Samsung

Número de pieza

componentes Descripción

Fabricante

AL1213A

8-BIT 0.5MSPS DAC

Samsung 

8-BIT 0.5MSPS DAC

TIMING DIAGRAM

AL1213A

D[0]-D[7]

90%

VOUT

50%

10%

DATA

Td

Tr

Ts

1LSB

Tf

D[0]-D[7]

PD

VOUT

+/- 1/2LSB

Tpon

Tpof

+/- 1/2LSB

1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition.

2. Settling time measured from the 50% point of full scale transition to the output remaining within ± 1/2 LSB.

3. Output rise/fall time measured between the 10% and 90% points of full scale transition.

FUNCTION DESCRIPTION

1. The AL1213A has a R-2R Ladder Block for 8bit and an Opamp Block for driving Output.

2. The R-2R Ladder Block generates binary weighted voltage (VRT/21 VRT/22 VRT/23 . . . VRT/2n)

corresponding to Digital Input Data for n-bit DAC and Output total voltage is summing of each values.

3. In Output voltage, MSB = VRT/21 LSB = VRT/2n

4. Output of the R2R Ladder Block is driven by Opamp

6

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