AG8888 Ver la hoja de datos (PDF) - ELAN Microelectronics
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AG8888 Datasheet PDF : 7 Pages
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AG8888
CALL WAITING DECODER
APPLICATION NOTE
1. VDD, GND
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog VDD pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the
respective GND's.
2. OE pin
Always connect OE to VDD for normal use.
3.
TIP
RING
C1
250V
3300p
R1
C2
250V
0.1u
R2
5.6k
180k
1N4148
C3
4700p
1N4148
C6
100p R4
R3
120k
R6
14 OPO
180k
1 TI/RI
56k R5
C4
2 BO
1M
4700p
C5
3 FI
4700p
In the application circuit above , some of the external element values are crucial. C2 value could not be less than
0.1uF. R2 = 5.6k is proper and you had better not to change it. The diode has to use Si type diode for noise
consideration.
There are an OP Amp. External resistors R3 and R4 can adjust the gain of OP Amp. The gain for OP Amp = -R4/
R3.
4. OPO pin
This pin is the gain adjustment of OP Amp. See the partial application above. For high frequency noise immunity,
the user can connect a 100pF capacitor between TI/RI pin and OPO pin.
5. OSCI pin, OSCI pin
The clock generator input XIN pin and output XOUT need to connect a feedback resistor 1M( between them for
proper operation.
6. About latch up
It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up due
to the voltage difference between AVDD and DVDD pins when power is ON.
* This specification are subject to be changed without notice.
8.8.2000 7
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