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ADP3203

2-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs

Analog Devices 

ADP3203

Pin

Mnemonic

1

HYSSET

2

DSHIFT

3

BSHIFT

4–8

VID[4:0]

9

BOM

10

DPSLP

11

DPRSLP

PIN FUNCTION DESCRIPTIONS

Function

Hysteresis Set. This is an analog I/O pin whose output is a fixed voltage reference and whose input

is a current that is programmed by an external resistance to ground. The current is used in the IC to

set the hysteretic currents for the core comparator and the current limit comparator. Modification

of the resistance will affect both the hysteresis of the feedback regulation and the current limit set-

point and hysteresis.

Deep Sleep Shift. This is an analog I/O pin whose output is the VID reference voltage and whose

input is a current that is programmed by an external resistance to ground. The current is used in the

IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by the

DPSLP signal. When activated, this added bias current creates a downward shift of the regulated

core voltage to a predetermined optimum level for regulation corresponding to Deep Sleep Mode of

CPU operation. The use of the VID code as the reference makes the deep sleep offset a fixed

percentage of the VID setting, as required by specifications.

Battery Optimized Mode (BOM) Shift. This is an analog I/O pin whose output is the VID

reference voltage and whose input current is programmed by an external resistance to ground. The

current is used in the IC to set a switched bias current out of the RAMP pin, depending on whether

it is activated by the BOM signal. When activated, this added bias current creates a downward shift

of the regulated core voltage to a predetermined optimum level for regulation corresponding to the

Battery Optimized Mode of the CPU operation. The use of the VID code as the reference makes the

BSHIFT a fixed percentage of the VID setting, as required by specifications.

Voltage Identification Inputs. These are the VID inputs for logic control of the programmed

reference voltage that appears at the DACOUT pin, and via external component configuration, is

used for setting the output voltage regulation point. The VID pins have a specified internal pull-up

current that, if left open, will default the pins to a logic high state. The VID code does not set

the DAC output voltage directly but through a transparent latch that is clocked by the BOM pin’s

GMUXSEL signal rising and falling edge.

Battery Optimized Mode Control (Active Low). This digital input pin corresponds to the

system’s GMUXSEL signal, which corresponds to Battery Optimized Mode of the CPU operation

in its active low state and Performance Optimized Mode (POM) in its deactivated high state. The

signal also controls the optimal positioning of the core voltage regulation level by offsetting it

downward in Battery Optimized Mode according to the functionality of the BSHIFT and RAMP

pins. It is also used to initiate a masking period for the PWRGD signal whenever a GMUXSEL

signal transition occurs.

Deep Sleep Mode Control (Active Low). This is a digital input pin corresponding to the system’s

STP CPU signal that, in its active state, corresponds to Deep Sleep Mode of the CPU operation,

which is a subset operating mode of either BOM or POM operation. The signal controls the optimal

positioning of the core voltage regulation level by offsetting it downward according to the functionality of

the DSHIFT and RAMP pins.

Deeper Sleep Mode Control (Active High). This is a digital input pin corresponding to the system’s

DPRSLPVR signal corresponding to Deeper Sleep Mode of the CPU operation. When the signal

is activated, it controls the DAC output voltage by disconnecting the VID signals from the DAC

input and setting a specified internal deeper sleep code instead. At deassertion of the DPRSLPVR

signal, the DAC output voltage returns to the voltage level determined by the external VID code.

The DPRSLPVR signal is also used to initiate a blanking period for the PWRGD signal to disable

its response to a pending dynamic core voltage change that corresponds to the VID code transition.

–6–

REV. 0

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