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74VCX1632245LB

16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR

STMicroelectronics 

74VCX1632245

16-BIT DUAL SUPPLY BUS TRANSCEIVER

LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR

s HIGH SPEED: tPD = 4.4ns (MAX.) at TA=85°C

VCCA = 3.0V VCCB = 2.3V

s LOW POWER DISSIPATION:

ICCA = ICCB = 20µA(MAX.) at TA=85°C

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOHA| = IOLA = 8mA MIN at

VCCA = 3.0V VCCB = 1.65V or 2.3V

|IOHA| = IOLA = 18mA MIN at

VCCA = 2.3V VCCB = 1.65V)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

s 26Ω SERIES RESISTOR ON A SIDE OUTPUTS

s OPERATING VOLTAGE RANGE:

VCCA(OPR) = 2.3V to 3.6V (1.2V Data

Retention)

VCCB(OPR) = 1.65V to 2.7V (1.2V Data

Retention)

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 16245

s LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

s ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

DESCRIPTION

The 74VCX1632245 is a dual supply low voltage

CMOS 16-BIT BUS TRANSCEIVER fabricated

with sub-micron silicon gate and five-layer metal

wiring C2MOS technology. Designed for use as an

interface between a 3.3V bus and a 2.5V or 1.8V

bus in a mixed 3.3V/1.8V,3.3V/2.5V and 2.5V/

1.8V supply systems, it achieves high speed

operation while maintaining the CMOS low power

dissipation.

This IC is intended for two-way asynchronous

communication between data buses and the

direction of data transmission is determined by

nDIR inputs. The enable inputs nG can be used to

disable the device so that the buses are effectively

isolated. The A-port interfaces with the 3V bus, the

B-port with the 2.5V and 1.8V bus.

All inputs are equipped with protection circuits

against static discharge, giving them 2KV ESD im-

munity and transient excess voltage. All floating

bus terminals during High Z State must be held

HIGH or LOW.

July 2003

TSSOP

TFBGA

µTFBGA

ORDER CODES

PACKAGE

TRAY

T&R

TSSOP48

74VCX1632245TTR

TFBGA54 74VCX1632245LB 74VCX1632245LBR

µTFBGA42 74VCX1632245TB 74VCX1632245TBR

LOGIC DIAGRAM

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