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27LV256

256K (32K x 8) Low-Voltage CMOS EPROM

Microchip Technology 

27LV256

FIGURE 1-2: PROGRAMMING WAVEFORMS

VIH

Address

VIL

VIH

Data

VIL

13.0V(2)

VPP

5.0V

6.5V(2)

VCC

5.0V

VIH

CE

VIL

VIH

OE

VIL

Program

Address Stable

tAS

Data Stable

tDS

tDH

tVPS

tVCS

High Z

Verify

tAH

Data Out Valid

tDF

(1)

tPW

tOPW

tOES

tOE

(1)

Notes: (1) tDF and tOE are characteristics of the device but must be accommodated by the programmer

(2) VCC = 6.5V ±0.25V, V PP = VH = 13.0V ±0.25V for express algorithm

TABLE 1-6: MODES

Operation Mode

Read

Program

Program Verify

Program Inhibit

Standby

Output Disable

Identity

X = Don’t Care

CE

OE

VIL

VIL

VIL

VIH

VIH

VIL

VIH

VIH

VIH

X

VIL

VIH

VIL

VIL

1.2 Read Mode

(See Timing Diagrams and AC Characteristics)

Read Mode is accessed when:

a) the CE pin is low to power up (enable) the chip

b) the OE pin is low to gate the data to the output

pins

VPP

A9

VCC

X

VH

X

VH

X

VH

X

VCC

X

VCC

X

VCC

VH

O0 - O7

DOUT

DIN

DOUT

High Z

High Z

High Z

Identity Code

For Read operations, if the addresses are stable, the

address access time (tACC) is equal to the delay from

CE to output (tCE). Data is transferred to the output

after a delay from the falling edge of OE (tOE).

© 1996 Microchip Technology Inc.

DS11020F-page 5

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