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VV6444C001

Low Cost Digital Camera (LCDC) Chipset

Vision 

STV0680A + VV6444/6410/6500

PRELIMINARY

Digital Camera Chipset; Customer Datasheet, Rev 3.0, March 2000

Figure 2 : SDRAM Read Timing (16Mbit device, burst read)

DCLK

CKE

Command

A0-9,BA

A10

DQM

DQ

tCK

tL

tH

tCMS tCMH

ACTIVE

WRITE

ROW

ROW

tAS

tAH

tCMS

NOP

COLUMN

PRECHARGE

NOP

tDS

tDH

tCMH

DIN M

DIN M + 1

DIN M + 2

DIN M + 3

tR C D

tRC

tRAS

tRP

Figure 3 : SDRAM Write Timing (16Mbit device, burst write)

Symbol Min Max Units

tCK 166.45 166.89 ns

tCH

½

tCK

tCL

½

tCK

tAC

½

tCK

tOH

0

ns

tCMS 82.88

ns

tCMH 82.85

ns

tAS

82.88

ns

Symbol Min

tDS

tDH

tRCD

tRAS

tRC

tRP

tRCD

tAH

81.01

83.41

1

5

7

2

1

82.76

Max

5

Units

ns

ns

tCK

tCK

tCK

tCK

tCK

ns

Table 7 : Timing parameters for SDRAM read/write

4.3.3 SDRAM refresh Period

The SDRAM refresh period from STV0680A is guaranteed to be no greater than 15.6µS during ‘Snapshot’/self-timer/continuous/

tethered video modes of operation (i.e. not standby mode). In standby mode, the SDRAM is set to self-refresh, therefore no

19

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CDSTV0680F-C

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