DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

VV6444C001 Ver la hoja de datos (PDF) - Vision

Número de pieza
componentes Descripción
Fabricante
VV6444C001 Datasheet PDF : 61 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
PRELIMINARY
Digital Camera Chipset; Customer Datasheet, Rev 3.0, March 2000
STV0680A + VV6444/6410/6500
4. STV0680A hardware interfaces
4.1 STV0680A pinout
The STV0680A pinout has been carefully developed to minimise the physical size of the support printed circuit board by
facilitating placement of and electrical routing to peripheral support components such as the SDRAM. The complete pinout and
listing is shown in Section 8.
4.2 Sensor interface
STV0680A uses a standard ST digital interface from the sensor, and the sensor clock input is provided by an output from
STV0680A. Designing a camera using this chipset should design as close as possible to the reference design (Section 9.), in
which case the chipset can be regarded as a functional ‘black box’, and no further details regarding the STV0680A-sensor
interface are required.
4.3 Memory interface
STV0680A is designed to interface to an external 16Mbit or 64Mbit SDRAM (see Table 4 and Table 5). The SDRAM device must
have a 16 bit wide data bus and operate from a 3.3V supply. Two sizes of SDRAM memory are supported by STV0680A, 16MBits
(1M x 16 bits wide) or 64MBits (4M x 16 bits wide), the memory size is auto-detected by STV0680A. STV0680A clocks the
SDRAM at 6MHz, typically this is well below the figures offered by most manufacturers’ devices. Devices which are PC66 and/or
PC100 compliant are preferred. For interface wiring, see Section 9.
4.3.1 SDRAM Current consumption
For maximum system battery life while no pictures are being taken, and to assist in meeting requirements for USB compliance, an
SDRAM should be chosen with the lowest possible self refresh current specification. For suggested SDRAM part numbers, see
Section 9.
4.3.2 SDRAM interface timing requirements
The following timing diagrams should be referred to when selecting SDRAM other than those recommended in Section 9.
DCLK
CKE
Command
A0-9,BA
A10
DQM
DQ
tCK
tL
tH
tCMS tCMH
ACTIVE
READ
ROW
ROW
tAS
tAH
tCMS
NOP
COLUMN
PRECHARGE
NOP
tAC
tO H
tCMH
tR C D
DOUT M
READ Latency
tRAS
DOUT M + 1
DOUT M + 2 DOUT M + 3
tRC
tRP
STV0680F_contents.fm
DQ sam ple
DQ sam ple
DQ sam ple
DQ sam ple
CDSTV0680F-C
18
Commercial in confidence

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]