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STV-5301-E01 Ver la hoja de datos (PDF) - Vision

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STV-5301-E01 Datasheet PDF : 51 Pages
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VV5301 & VV6301
Introduction
2.3.3 2-wire Serial Interface
The 2-wire serial interface provides complete control over sensor setup and operation. Two serial interface broadcast addresses
are supported. One allows all sensors to be written to in parallel while the other allows all sensors and co-processors to be written
to in parallel.
Section 8. defines the serial interface communications protocol and the register map of all the locations which can be accessed
via the serial interface.
2.4 Other Features
2.4.1 Tristating Digital Outputs
The QCK, FST and Databus[7:0] pins can be tristated. The QCK pin can be independently tristated by driving the QCKTRI pin
low. The QCK, FST and upper nibble of the Databus can also be tristated via a serial register control bit, see register[116] for
more details. The lower nibble of the Databus can also be independently tristated using a different control bit in register[116].
2.4.2 Synchronising Video Timing
The video timing logic in VV5301/VV6301 can be synchronised, i.e. reset to the beginning of a timing field, by an external pin,
SIN. This pin is normally low. To enable the synchronising feature the user must drive the pin high for a number of clock periods,
c.10 CLKI periods, then drive it low again. This synchronisation should only be done every other field as the sensor has a 2 field
repeat cycle requirement for the video timing. If the SIN pin was asserted every field the exposure controller and application of
new external exposure and gain settings would not operate correctly.
2.4.3 Pixel Hold Feature
The HPIX signal can be used to freeze the internal ADC, forcing the sensor to stop converting new pixel values. If the HPIX is
driven high then the ADC will maintain the currently converted pixel value. This feature is intended to function as an external pixel
defect correction system, albeit a ver basic example.
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cd5301_6301f-3-0.fm
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