VV6801 Ver la hoja de datos (PDF) - Vision

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VV6801

High resolution CMOS 1300K Pixel Image Sensor with support for external FPN cancellation and serial interface control, available in colour (VV6801) and monochrome (VV5801) versions.

Vision 

VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1

AVO

Black

SELRef

CLAMP

Peak

White

CLAMP

SELRef

VRT

Pixel Array

+ Columns

8x8

Pixels

2:1

AVO

ryVCL1

VCL2

ina AVORef

SAMRef

Black Reference

lim Figure 2.7 : Analogue output circuit

The sensor’s internal black reference, which drives the AVORef output path, is derived from a separate 8 by

8 array of pixels connected in parallel. The input voltage to all pixels in the 8 by 8 array is VRT, that is the

pixels are in reset. A sample & hold stage controlled by SAMRef allows the VRT voltage driving the black

e reference pixels to be sampled, freezing the black reference value.

r Normally the black level reference should be updated between every still image capture sequence or

between every frame in live video mode. Under very high illumination, however, the black reference should

P be sampled between every line in live video mode.

The internal black reference can be sampled at the beginning of a frame using SAMRef. It can also be

observed line by line by asserting SELRef (without CLAMP) in the dead period between reading rows of

pixels out onto AVO.

2.8 The 5-Bit DAC

The internal five bit resistive ladder DAC is energised by a Bias Generator that is set by the internal Bandgap

Voltage Reference, Vbg, and the external 12K resistor connected from Rset to AGND. The Vdac output of

the DAC, which can be used to set either VCL1 or VCL2, is adjusted by bits 11 to 15 of the Control Register/

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VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1

Serial Interface.

AVCC

I = Vbg/122R

R ~ 100 Ohms

Bias

Generator

Vbg

Rset

12K

CR[15..11]

y 32

r 5-Bit DAC

Vdactop

Vdac

limina 176R

AGND

Vdac3/4

Vdacbot

eFigure 2.8 : 5 bit DAC

r Parameter

Definition

Value

P Vdactop

208/122 * Vbg

2.08V

Comment

Vdacbot

176/122 * Vbg

1.76V

Vdac3/4

199/122 * Vbg

1.99V

Vdac

CR[15..11] * (32/122 * Vbg)

-

Zdac

Vdac Output Impedance

21K

Ohms ±25%

Table 2.1 : 5-Bit DAC Parameters

Note: The Vbg pin is a high impedance output, and can be over-ridden within the VCL input limits.

2.9 Black Reference Lines

There are six lines at the bottom of the pixel array that are covered with opaque masking. These black

reference lines have their own reset shift register. A four to one multiplexer, controlled by Control Register

bits CR[4] and CR[3], selects the input to this shift register (FBCK), and hence the operating mode. The four

modes of operation are:

1. Permanent Reset - By setting FBCK low, the black lines are permanently reset to VRT.

2. Minimum Integration - FBCK follows the field read pulse, FR; the black reference lines are held in min-

imum exposure.

3. Integration - FBCK follows the field read pulse, FI; the black reference lines therefore have the same

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