VV6801 Ver la hoja de datos (PDF) - Vision

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VV6801

High resolution CMOS 1300K Pixel Image Sensor with support for external FPN cancellation and serial interface control, available in colour (VV6801) and monochrome (VV5801) versions.

Vision 

VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1

2.4 Pixel Readout Architecture

Bitline Test/Clamp Circuitry

VRT

LCK

Reset[n]

Read[n]

bit-line, Vx[m]

Pixel[m,n]

y Dpix Cpix

inar Pixel Array

EVEN

PXRD

CDSR

VSETB

VCLRB

Vbloom

COLsam

Output

Channel

ColumSonur[cme F]ollower

lim Sample/Hold circuit

Sample/Hold

eOutput Channel 0

rOutput Channel 1

POutput Channel 2

Read[m]

SAMRef VRT

Line Reference

Clamp

Output Channel 3

CSe[401:0]

CSo[401:0]

EC

EC

CLAMP

CS[401:0]

Output

Stage

LS

Horizontal Shift Register

AVO AVORef

Figure 2.5 : Pixel Readout Schematic

2.5 Video Output

The four-PCK long LS pulse initiates output of a line of video, with the first valid pixel being sampled after LS

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falls, and subsequent pixels appearing at AVO as LS propagates along the Horizontal Shift Register. The

AVO output for each pixel should then be sampled as close to the end of the PCK cycle as possible to allow

maximum settling time.

PCK

PCK [R]

changes pixel

LS

on AVO

PCK [R]

Samples LS

AVO

First Valid pixel after

ry LS is sampled

¼ PCK max. @ 5MHz

AVO output has settled

ina Figure 2.6 : Pixel Level Sampling

2.6 The Video Output Chain

At the top of each column of the array is a sample and hold stage (controlled by COLsam), which drives the

output stage. The purpose of the sample & hold is to ensure that all the pixels in a line have the same

lim exposure, as the outputs of a row of pixels are sampled at the same instant. If COLsam is not used then each

pixel will carry on integrating until it is read out. Therefore, since all pixels within a line are released from reset

at the same time, each pixel will have a different integration time, and hence exposure value.

The columns are read out via four output channels. Each channel is multiplexed onto the AVO pin via an AC

e coupling stage to restore the DC content. The AVORef pin provides a pseudo-differential output, obtained

from an internal black reference. (The pseudo-differential output stage cancels out leakage across the

r coupling capacitors since both output channels experience the same rate of decay.)

P Note: The video at AVO is ‘inverted’, that is Black is higher than White.

2.7 AVO Reference

The DC content of the output stage is set by using the SELRef signal to simultaneously put the internal

reference on the AVO and AVORef output channels, and then the CLAMP signal to charge the amplifier side

of the coupling stages to VCL1 and VCL2 respectively. The integrated 5-bit DAC, controlled by Control

Register bits CR[15..11], can be used to adjust one or other of these clamping voltages. The CLAMP signal

must fall before SELRef falls. The AC Coupling Capacitors must be refreshed at least once every still image

capture sequence, or every frame of a live video.

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