VV5801B001 Ver la hoja de datos (PDF) - Vision
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VV5801B001 Datasheet PDF : 23 Pages
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VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1
2.2 Reset and Read Vertical Shift Registers
The resetting and reading of pixels is performed on a line by line basis, that is a row of column amplifiers
reads a whole line of pixel voltages in parallel. The reset/integrate/read cycle for a line of pixels is controlled
by the Reset Vertical and Read Vertical shift registers (VSRs).
The length of the ‘Frame Integrate’ pulse, FI, propagating along the Reset Vertical shift register sets the pixel
integration time. FI going high at a point along the VSR releases that line of pixels from RESET, starting the
integration period. The two-line ‘Frame Read’ pulse, FR, which comes at the end of the integrate period,
starts the field readout, which proceeds from ‘bottom’ to ‘top’. As FR propagates along the Read Vertical shift
register, it controls which line is to be read. For exposure control by means of a shutter mechanism, FI should
be held high throughout the frame integrate/read cycle.
The Vertical Shift Registers are clocked by the Line Clock pulse, LCK. Within a frame, first an even line, then
an odd line is read. This is controlled by the EVEN clock, which must be half the LCK frequency and change
two PCKs before LS (Line Start) rises. A pair of lines may be ‘skipped over’ (for example as in ‘Horizontal
Cine’ mode—See Section 2.3), by inserting two LCK pulses and one EVEN pulse between line readout
y sequences. .
ar LCK
EVEN
in FI
FR
lim AVO
Exposure
AVO Not Valid
1306 Lines
Black Ref Line
Valid Video Line
e Figure 2.2 : Relative timing for single frame integration and readout
r Note: If FR does not rise with the rising edge of EVEN, that is if EVEN is high during the second line period
P of the FR pulse, the AVO-valid line readout sequence is offset by one line.
Further control of the VSRs is effected by: VCLRB (Clear Reset and Read); VSETB (preset Reset to ones);
CDSR (reset row, but do not advance VSRs). The PXRD input to the Read VSR enables a line of pixels to
be read out. (See Section 5. and Section 7.5 for more details.)
The first six lines in the array are black reference lines. The reset/integrate cycle for these lines is controlled
by a third shift register, defined by bits CR[4] and CR[3] in the Control Register (See Section 6.). This shift
register can either hold the black reference lines in permanent reset, allow minimum exposure or have the
same integration time (exposure) as the rest of the array.
The readout sequence, initiated by FR going high, is therefore: six black lines followed by eight colour
characterisation lines, 2 ‘dummy’ line, 1280 valid video lines, 2 further ‘dummy’ lines, eight further colour
characterisation lines.
With any of the three ‘Vertical Cine’ modes enabled, the six black reference lines are always read out, but
the rest of the array is subsampled (subsampling commences with the colour characterisation lines at the
bottom of the array), e.g. with Vertical Cine enabled to carry out 1/2 subsampling (see Section 5.4.2), this
becomes: six black lines, four colour characterisation lines, 2 dummy lines, 640 valid video lines, and a further
four colour characterisation lines.
Note: ‘Vertical Cine Mode’ is a new feature on the VV6801. On the VV6850/5850, this feature is not available,
therefore line skipping timing schemes would be required to achieve the same vertical subsampling effect as
Vertical Cine Mode provides on the VV6801/5801. See Section 5.4.2 and Section 6.5.
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VISION VV6801/5801 PRELIMINARY CUSTOMER DATASHEET Rev 1.1
2.3 Horizontal Shift Register
The Horizontal Shift Register is clocked by the Pixel Clock, PCK. Columns are read out, from left to right, by
the Line Start pulse, LS, propagating along the Horizontal Shift Register. The LS pulse must be four PCK
periods long, with the first valid pixel being sampled after the falling edge (see Section 7. for exact
relationship). To avoid bandwidth limitations within the output stage causing cross talk problems between the
colours in a colour pixelated sensor, the horizontal shift register either reads out the odd or the even columns,
under control of the EC signal.
In order to read valid pixel data, the Pixel Read input to the Read VSR, PXRD, must be pulsed high, as shown
in Figure 2.3. When reading out either the even columns (EC=1) or the odd columns (EC=0) it is the central
512 pixels of the 514 pixels read out that are valid. In Horizontal Cine mode (Selected with bit CR[3] in the
Control Register), every second pixel within a row is read out; of the 258 pixels read out for either EC=1 or
EC=0, the central 256 pixels are valid. To preserve the correct aspect ratio, Vertical Cine mode can be
enabled to skip every second line pair, as shown in Figure 2.4.
Note: ‘Horizontal Cine Mode’ on VV6801/5801 performs the same function as ‘Cine Mode’ on the VV6850/
y 5850.
ar LCK
in EVEN
Even line
Odd Line
PXRD
AVO
LS
EC
Even pixels Odd pixels
Even pixels Odd pixels
lim Figure 2.3 : Relative line readout timing (Full Resolution)
PreEven line (0)
Odd Line (1)
Even line (4)
Odd
Line (5)
LCK
EVEN
PXRD
AVO
LS
Even Odd
Even Odd
Even Odd
EC
Sensor timing skips two lines
Figure 2.4 : Relative line readout timing (Horizontal Cine Mode and 1/2 Vertical Cine
mode enabled)
The HCLRB input (active low) clears the HSR to all zeros. HCLRB can also be used, for example,
to prematurely end a line scan, perhaps when only part of the image is required.
Note: The power-on reset signal, RSTB, can be used to drive HCLRB (and VCLRB for the Vertical
Shift Registers) at power up.
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