7.10 Level selector
Level Selector is a control of the display synchronization. Display voltage can be separated into
two sets and used with different cycles. Synchronization is important since it selects the
required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD
waveform.
7.11 HV Buffer Cell (Level Shifter)
HV Buffer Cell works as a level shifter which translated the low voltage output signal to the
required driving voltage. The output is shifted out with an internal FRM clock, which comes
from the Display Timing Generator. The voltage levels are given by the level selector, which is
synchronized with the internal M signal.
For a panel with N rows and M columns, the optimal LCD driving voltage are given as:
( ) VL7 −VL4 = VL4 −VSS =
N
4
×
2
N
N −1
×Vth
( ) VL6
− VL4
= VL4
− VL 2
=
4×
VL7 −VL4
N
And
VL5
− VL 4
= VL4
− VL 3
=
VL6
− VL 4
2
where:
Vth is the threshold voltage of the LCD panel
VL7 is the maximum (Row) driving level with reference to VSS
(The peak-to-peak Row driving voltage is given by VL7-VSS)
VL4 is the middle of all driving levels
VL6, VL5, VL3 and VL2 are the other Column driving levels
(The peak-to-peak Column driving voltage is given by VL6-VSS)
Relationship between the levels:
VL7 > VL6 > VL5 > VL4 > VL3 > VL2 > VSS
and
VCC > VL4 + 2V
SSD1854
Series
Rev 1.0
08/2002
14
SOLOMON