SSD0858Z Ver la hoja de datos (PDF) - Solomon Systech

Número de pieza

componentes Descripción

Fabricante

SSD0858Z

LCD Segment / Common Driver with Controller

Solomon Systech  

7 FUNCTIONAL BLOCK DESCRIPTIONS

7.1 I2C communication Interface

The IIC communication interface consists of slave address bit (SA0), I2C-bus data signal (SDA)

and I2C-bus clock signal (SCL). Both the SDA and the SCL must be connected to pull-up resistors.

There is also an input signal RES which is used for the initialization of device.

a) Slave address bit (SA0)

SSD0858 has to recognize the slave address before transmitting or receiving any information by the

I2C-bus. The device will responds to the slave address following by the slave address bit (“SA0” bit)

and the read/write select bit (“R/W” bit) with the following byte format,

b7 b6 b5 b4 b3 b2 b1 b0

0 1 1 1 1 0 SA0 R/W

“SA0” bit provides an extension bit for the slave address. Either “0111100” or “0111101” can be

selected as the slave address of SSD0858.

“R/W” bit determines the I2C-bus interface is operating at either write mode or read status mode.

b) I2C-bus data signal (SDA)

SDA acts as a communication channel between the transmitter and the receiver. The data and the

acknowledgement are sent through the SDA.

It should be noticed that the ITO track resistance and the pulled-up resistance at “SDA” pin becomes

a voltage potential divider. As a result, the acknowledgement would not be possible to attain a valid

logic 0 level in “SDA”.

c) I2C-bus clock signal (SCL)

The transmission of information in the I2C-bus is following a clock signal, SCL. Each transmission of

data bit is taken place during a single clock period of SCL.

7.2 Command Decoder

Input is directed to the command decoder based on the input of control byte which consists of a

D/C bit and a R/W bit. For further information about the control byte, please refer to the section

“I2C-bus write data and read register status” on page 22. If both the D/C bit and the R/W bit are

low, the input signal is interpreted as a Command. It will be decoded and written to the

corresponding command register. If the D/C bit is high and the R/W bit is low, input signal is written

to Graphic Display Data RAM (GDDRAM).

7.3 Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size

of the RAM is 104 x 65 x 2 = 12,480bits. Figure 4 is a description of the GDDRAM address map.

For mechanical flexibility, re-mapping on both Segment and Common outputs are provided.

For vertical scrolling of display, an internal register storing the display start line can be set to

control the portion of the RAM data mapped to the display. Figure 4 shows the case in which the

display start line register is set at 30H.

For those GDDRAM out of the display common range, they could still be accessed, for

either preparation of vertical scrolling data or even for the system usage.

7.4 Oscillator Circuit

This module is an On-Chip low power RC oscillator circuitry (Figure 3). The oscillator generates the

clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.

SSD0858

Rev 1.0

11/2002

12

SOLOMON

Share Link: