DM9081 Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.

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DM9081

10 BASE-T hub controller

Davicom Semiconductor, Inc. 

DM9081

10BASE-T Hub Controller

Jabber Lockup Protection

Reset

The DM9081 chip implements a built-in jabber

protection scheme to ensure that the network is not

disabled due to transmission of excessively long data

packets. This protection scheme will automatically

interrupt the transmitter circuits of the DM9081 for

96-bit times if the DM9081 chip has been transmitting

continuously for more than 65,536-bit times. This is

referred to as MAU Jabber Lockup Protection

(MJLP).

An internal circuit ensures that a minimum reset

pulse is generated for all internal circuits. For a

RESET input with a slow rising edge, the input buffer

threshold may be crossed several times due to

ripples on the input waveform. During reset, the

output signals are placed in their inactive states. This

means that all analog signals are placed in their idle

states, bidirectional signals are not driven, active

LOW signals are driven HIGH, and all active HIGH

signals and the LED_LATCH pin are driven LOW. In

a multiple DM9081 chip repeater, the RESET signal

should be applied simultaneously to all DM9081

chips, and should be synchrononized to the external

X2 clock. Table 1 summarizes the state of the

DM9081 chip following reset.

Function

DAT

Transmitters (TP and AUI)

RECEIVERS (TP and AUI)

AUI Partition/Reconnection

TP Port Partition/Reconnection

LINK Test Function for TP Ports

Active Low Output

Active High Output

State after Reset

Hi-Impedance

Idle

Enabled

Reconnect

Reconnect

Enabled

High

Low

Pull Up/Pull Down

NO

NC

Terminate

N/A

N/A

N/A

NO

NO

Table 1. Initial State of DM9081

Expansion Port

The DM9081 chip expansion port is comprised of

three pins: a bi-directional signal (DAT), an input

signal (EXPIN#), and an output signal (EXPOUT#).

These signals are used for multiple-DM9081 chip

repeater applications. In this configuration, all

DM9081 chips must be synchronized with a common

clock connected to the X2 inputs. An external

synchronnous reset is required. The DM9081

expansion scheme allows the use of multiple

DM9081 chips in either a single repeater or a

modular multiple repeater with backplane

architecture. The DAT pins of all DM9081 chips must

be interconnected. The DAT pin is a bidirectional I/O

pin that can be used to transfer data or a jam signal

between the DM9081 chips. The data sent over the

DAT line is in NRZ format, and is synchronized to the

common clock.

In the multiple DM9081 configuration, the DM9081

chip asserts the EXPOUT# pin to indicate that it is

active and is ready to drive the DAT pin. An external

logic senses the EXPOUT# line from all the DM9081

chips and asserts the EXPIN# line to each DM9081.

The active DM9081 asserts EXPOUT#, and sends

data or jam on the DAT line. Other inactive DM9081

detect EXPIN# asserted, and receive data on the

DAT line. If more than one DM9081 chip asserts

EXPOUT# lines, then all DM9081s will broastcast

jam signals.

Final

7

Version: DM9081-DS-F02

February 02, 2001

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