DM560P Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.

Número de pieza

componentes Descripción

Fabricante

DM560P

V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set

Davicom Semiconductor, Inc. 

DM560P

V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set

Auto-configuration Register: Address F400H

(continued)

* When a reset condition occurs, the I/O and

Interrupt configuration registers must be reset to the

default value according to bit 0 - bit 5.

RxDataBits Register: Address DC00H

Write only

Once the RxDataBit set to 1, the data in the RxBuffer

will be transferred to RxFiFo. The transfer bit number

is the same as the programming value ofRxDataBits

Register.

RxBuffer: Address DC01H

Write only

Receive data will be written to the RxBuffer and will

be input to the RxHDLC circuit. The RxBuffer is 16

bytes wide.

RxFiFo: Address DC01H

Read only

After the data has been passed from the RxBuffer to

the RxHDLC circuit, the RxHDLC circuit will remove

the 7eH patterns and transfer the results to the

RxFiFo. There RxFiFo is 21 bytes wide.

TxDataBits Register: Address DC02H

Write only

Data written to TxDataBits will be presented to the

TxFiFo. The data in TxFiFo will be transferred to

TXHDLC circuit. The transfer bit number is the same

as the value of TxDataBits register. If the TxFiFo is

empty, a 7e pattern will be loaded to the TxFiFo. If

TxFiFo is not empty and the data frame has the

pattern of five consecutive “1” , then the TXHDLC

circuit will insert “0” automatically.

TxFiFo Register: Address DC03H

Write only

The original HDLC frame data will be loaded to the

TxFiFo, presented to the input of the TxHDLC circuit.

The TxFiFo is 21 bytes wide.

TxBuffer: Address DC03H

Read only

According to TxDataBits, the TxHDLC circuit will

transfer the same number data bits to the TxBuffer.

The TxBuffer is 16 bytes wide.

HDLC CNTL/STATUS Register: Address DC04H

Bit0: TxReady0

0: indicates the data in the TxFiFo has deceased

to zero and the HDLC circuit has transferred

the 1st 7eH pattern.

1: indicates that the TxFiFo data is greater than or

equal to the threshold value.

Bit1: Rxdata

0: all the data in the RxBuffer has been read.

1: Programed by software to indicate that all data

in the RxDataBits register has been written to

the RxBuffer.

Bit2: TxFiFo Threshold

0: TxFiFo threshold No. = 11

1: TxFiFo threshold No. = 16

Bit3: TxFiFo Status

0: data No. in TxFiFo >= threshold

1: data No. in TxFiFo <= threshold

Bit4: Txdata

0: A write action to TxDataBites register will clear

this bit.

1: Bit No. in TxBuffer = TxDataBits register.

Bit5: RxFiFo empty

0: data bytes No. in RxFiFo <>0

1: data bytes No. in RxFiFo = 0

Bit6: Reset

0: Normal state

1: reset HDLC circuit

In_ buffer register: Address DC08

write only

Controller write the original data to this temp buffer.

Out _ buffer register: Address DC08H

read only

Controller read the result data from this buffer

Status/Rst register: Address DC09H

Bit0: data ready flag (read only)

1: data has been load to out _ buffer. (clear

automatically by a read from out_ buffer)

0: data hasn’t been load to out _ buffer.

Bit1: frame end flag (read only)

1: Indicate end of HDLC frame (clear by a reset

action)

Bit2: fram ready flag (read only)

1: CRC check ok.

0: CRC check fail.

Bit3: In _ buffer empty flag

10

Preliminary

Version: DM560P-DS-P07

August 11, 2000

Share Link: