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FS612509-01 Datasheet PDF : 9 Pages
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FS612509-01/-02
1:9 Zero-Delay Clock Buffer IC
Table 7: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX. UNITS
Overall
Skew, Output to Output *
Skew, Tracking *
tsk(o)
Measured on the rising edge at 1.65V; CL = 15pF
Measured using a –0.5% 31.5kHz spread
spectrum reference clock at 133.33MHz
Static Phase Error *
From rising edge on CLK to rising edge on FBIN
Clock Stabilization Time *
Time required for the PLL to achieve phase lock
Loop Bandwidth *
For calculation of Tracking Skew
Phase Angle *
For calculation of Tracking Skew
Clock Outputs (1Y0:4, 2Y0:3, FBOUT)
Duty Cycle *
dt
Ratio of high pulse width to one clock period,
measured at 1.65V
45
Jitter, Cycle-Cycle *
Jitter, Period (peak-peak) *
Rise Time *
Fall Time *
Enable Delay *
Disable Delay *
tj(CC)
Adjacent cycles at 1.65V
-75
tj(∆P)
From rising edge to next rising edge at 1.65V
tr
VO = 0.4V to 2.0V; CL = 15pF
tf
VO = 2.0V to 0.4V; CL = 15pF
tDLH
via 1G or 2G
1
tDHL
via 1G or 2G
1
-120
150
150
3
1.2
-0.031
ps
ps
ps
ms
MHz
°
55
%
+75
ps
1.2
ns
1.4
ns
10
ns
10
ns
Figure 3: Clock Skew Measurement
Figure 4: Phase Error Measurement
Any
output
50% VDD
clock skew (tsk(o))
Any
output
50% VDD
CLK 50% VDD
phase error
FBIN
50% VDD
Figure 5: Timing Measurement Points
tr
tf
3.3V
2.4V
50% VDD
0.4V
dt
Figure 6: Output Enable Measurement
VDD
Output
Enable
50%
50%
VSS
Output
10%
tDLZ
90%
tDHZ
50%
VOL
tDZL
VOH
50%
tDHZ
ISO9001
QS9000
7
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